In a system in which active and standby units, each used to control a VCXO on the basis of a reference signal from a GPS receiver to generate a high-precision clock, constitute a redundant arrangement, and a clock is output from the active unit, a clock generating circuit has an arrangement in which when the active unit cannot receive any reference signal from the GPS receiver for some reason, free-running operation is performed in the control state the VCXO assumed when the reference signal stopped in the internal circuit of the active unit, and switching to the standby unit is not immediately performed, and an arrangement in which when the standby unit can normally receive the reference signal from the GPS, the output clock from the active unit during free-running operation is monitored, and the unit that is to receive the reference signal is switched from the active unit to the standby unit at the timing at which no influence is exerted on the output clock when a phase difference larger than a predetermined value is detected between the output clock and the reference signal from the GPS receiver of the standby unit, thereby preventing a clock exceeding the phase difference allowed in the system from being supplied to another circuit.

Clock generation circuit

The music-on-hold card is replaced by another card (16A) comprising a microprocessor (17), a comparator (20), a timer (25) and a bistable flip-flop (28). In the event that there is no music-on-hold being output (15) by the microprocessor (17), this inadequate audio level is detected by the comparator (20) and the timer (25), this triggering the bistable (28) and causing via the input (30) of the microprocessor the replacement of the deficient music-on-hold by a standby tone.

Security device for telephone installation with music on hold.

The method involves using two clock generators of which the first clock generator generates clock signals in synchronisation to a connected reference clock source and provides the signals to the second clock generator. The second clock generator generates clock signals in synchronisation to the clock signals provided by the first generator. The second clock generator generates clock signals in synchronisation to the clock signal of a reference clock source and provides the clock signals to the first clock generator when the second clock generator detects that the clock signals from the first clock generator are disturbed. The first clock generator generates the clock signals in synchronisation to the clock signals provided by the second clock generator, when the first clock generator detects clock signals provided by the second clock generator.

Electrical circuit with clock generator for generating an internal clock and corresponding method

The invention relates to a method and a circuit BA for monitoring the frequency stability of an SDH network equipment clock generator fixed frequency local oscillator LO and for generating an alarm indication Al in case the frequency drift or fluctuation of said local oscillator LO exceeds a specified value with respect to a reference frequency signal input RO_I coming from a remote oscillator. It also relates to a redundant circuit arrangement for monitoring the frequency stability of two redundant SDH network equipment clock generator circuits; an to an SDH equipment clock generator circuit and an SDH network element comprising the circuit BA described above.

A method of monitoring the frequency stability of an oscillator used for network element clock generation and generating an alarm indication

La carte de musique de patience est remplacee par une autre carte 16A comportant un microprocesseur 17, un comparateur 20, un temporisateur 25 et une bascule bistable 28. En cas d'absence de musique de patience en sortie 15 du microprocesseur 17, ce niveau audio insuffisant est detecte par le comparateur 20 et le temporisateur 25, ce qui fait basculer le bistable 28 et entraine par l'entree 30 du microprocesseur le remplacement de la musique de patience defaillante par une tonalite d'attente.

Dispositif de securite pour installation telephonique a musique de patience

In a system where timing is supplied with a stand-by generator (PLL), a corresponding arrangement of a plurality of monitoring circuits (OA; OB) and arrangements of connector/changeover switches (A/U) enables the functional capacity of the monitoring circuits to be self-checked, and, in routine testing, independent of the switch setting of a changeover device which operates when a generator is switched from stand-by mode to active mode and vice versa, it is always the same generator which acts on the distribution sub-system (V0, 1).

Circuit arrangement for routinely testing the timing distribution of a plurality of units operated with the same timing

A circuit configuration for the routine testing of the clock supply of a large number of digital TDM telecommunication units operated with the same clock, wherein a clock supply with stand-by generator through a corresponding arrangement of several monitor circuits and arrangements of on/alter switches, the operatability of the monitor circuits themselves can be tested so that on routine testing independent of the switching position of a change-over switching device effective upon switching a generator from stand-by operation to active operation respectively the same generator always acts upon the partial distribution system.

Ernst Wolfram Dipl Ing

Papers

Circuit arrangement for routinely testing the timing distribution of a plurality of units operated with the same timing

Circuit configuration for routine testing of the clock supply of a large number of units operated with the same clock