A more efficient method of handling instructions in a computer processor, by associating resource fields with respective program instructions wherein the resource fields indicate which of the processor hardware resources are required to carry out the program instructions, calculating resource requirements for merging two or more program instructions based on their resource fields, and determining resource availability for simultaneously executing the merged program instructions based on the calculated resource requirements. Resource vectors indicative of the required resource may be encoded into the resource fields, and the resource fields decoded at a later stage to derive the resource vectors. The resource fields can be stored in the instruction cache associated with the respective program instructions. The processor may operate in a simultaneous multithreading mode with different program instructions being part of different hardware threads. When the resource availability equals or exceeds the resource requirements for a group of instructions, those instructions can be dispatched simultaneously to the hardware resources. A start bit may be inserted in one of the program instructions to define the instruction group. The hardware resources may in particular be execution units such as a fixed-point unit, a load/store unit, a floating-point unit, or a branch processing unit.

Instruction group formation and mechanism for SMT dispatch

PROBLEM TO BE SOLVED: To provide a data processor and a method for optimizing the performance of a compiled application code. SOLUTION: The data processor is provided with a processor 130 and a compiler 110 which compiles the application code 100 for generating an instruction executed by the processor 130. Furthermore, a non-invasive trace unit 300 is coupled to the processor 130 for generating trace information indicating the instruction executed by the processor from an input signal received from the processor 130. The compiler 110 is then constituted so as to control the compilation of the application code 100 according to the trace signal. The non-inverse nature of the trace unit 300 is enabled to generate the trace signal for producing profiling information for use by the compiler 110 without changing the behavior of the code executed by the processor 130. Thus, the profiling information used in a feedback driven optimization compilation system is obtained. COPYRIGHT: (C)2004,JPO

Compilation of application code in data processor

PROBLEM TO BE SOLVED: To provide a device for sampling many potentially simultaneous instruction in a processor pipeline. SOLUTION: This device is the one which samples many simultaneous execution instructions in a processor pipeline of a system 100 and a pipeline 111 has plural processing steps. This device identifies the plural instructions to be selected when the instructions are fetched to the pipeline 111. Plural selected subsets of the instructions are simultaneously executed in the pipeline 111. While any of the plural selected instructions is at any step of the pipeline 111, the state information of the system is sampled. When all the selected instructions go out of the pipeline, software is notified of it and therefore, the software can read any state information.

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Device for sampling many potentially simultaneous instructions in processor pipeline

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Papers

Device for sampling many potentially simultaneous instructions in processor pipeline

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