This review describes recent groundbreaking results in Si, Si/SiGe, and dopant-based quantum dots, and it highlights the remarkable advances in Si-based quantum physics that have occurred in the past few years. This progress has been possible thanks to materials development of Si quantum devices, and the physical understanding of quantum effects in silicon. Recent critical steps include the isolation of single electrons, the observation of spin blockade, and single-shot readout of individual electron spins in both dopants and gated quantum dots in Si. Each of these results has come with physics that was not anticipated from previous work in other material systems. These advances underline the significant progress toward the realization of spin quantum bits in a material with a long spin coherence time, crucial for quantum computation and spintronics.

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Silicon quantum electronics

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices.

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Overview of emerging nonvolatile memory technologies

We are inspired by the beauty and simplicity of self-organizing materials and the promise they hold for enabling continued improvements in semiconductor technology. Self assembly is the spontaneous arrangement of individual elements into regular patterns," under suitable conditions, certain materials self organize into useful nanometer-scale patterns of importance to high-performance microelectronics applications. Polymer self assembly is a nontraditional approach to patterning integrated circuit elements at dimensions and densities inaccessible to traditional lithography methods. We review here our efforts in IBM to develop and integrate self-assembly processes as high-resolution patterning alternatives and to demonstrate targeted applications in semiconductor device fabrication. We also provide a framework for understanding key requirements for the adoption of polymer self-assembly processes into semiconductor technology, as well as a discussion of the ultimate dimensional scalability of the technique.

Polymer self assembly in semiconductor microelectronics

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

https://ir.nctu.edu.tw:443/bitstream/11536/15375/1/000298968600016.pdf

Developments in nanocrystal memory

A method of discharging a charge storage location of a transistor of a non-volatile memory includes applying first and second voltages to a control gate and a well region, respectively, of the transistor. The first voltage is applied to the control gate of the transistor, wherein the control gate has at least a portion located adjacent to a select gate of the transistor. The transistor includes a charge storage location having nanoclusters disposed within dielectric material of a structure of the transistor located below the control gate. Lastly, a second voltage is applied to the well region located below the control gate. Applying the first voltage and the second voltage generates a voltage differential across the structure for discharging electrons from the nanoclusters of the charge storage location.

Nonvolatile memory and method of making same

A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.

Split gate memory cell and method therefor

A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.

Program and erase in a thin film storage non-volatile memory

A memory device is formed on a semiconductor substrate. A select gate electrode and a control gate electrode are formed adjacent to one another. One of either the select gate electrode or the control gate electrodes is recessed with respect to the other. The recess allows for a manufacturable process with which to form silicided surfaces on both the select gate electrode and the control gate electrode.

Erwin J. Prinz

Papers

Nonvolatile memory and method of making same

Split gate memory cell and method therefor

Program and erase in a thin film storage non-volatile memory

Silicided nonvolatile memory and method of making same

Silicon nanocrystal non-volatile memory for embedded memory scaling