Error injection has become critically important for testing the reliability of newly designed hardware systems. Evaluating how a design under test (DUT) reacts to different error-injection methodologies is essential for verification engineers to design dependable universal verification methodology (UVM) scoreboards for error-detection purposes. The first main contribution of this paper is to decide on the feasibility and compatibility of some error-injection techniques when used with networks-on-chip (NoC) platforms for simulation and hardware emulation environments. We target a UVM-based error-injection and detection environment with reusable components. Proposed techniques, introducing both positive and negative test scenarios, are applied to two examples of NoC components: 1) a base router and 2) Daniel router. Base router is a simple case study to prove proposed schemes, whereas Daniel router is a complex reconfigurable open-source case study. Daniel router provides the ability to change router architecture with some parameters and applied algorithms. The second main contribution of this paper is to integrate a full UVM environment with various verification approaches. Target approaches include error injection and detection using reusable and generic UVM environment and components for NoC. Network response is inspected according to error type and methodology. Finally, the proposed UVM environment is used to test and verify an ${N}\,\,{\times }\,\,{N}\,\,2$ -D network composed of base routers or Daniel routers.

On Error Injection for NoC Platforms: A UVM-Based Generic Verification Environment

The Heterogeneous Network-on-Chip (HNoC) integrates CPU cores, Graphic Processing Unit (GPU) cores, last-level-cache and memory controllers. The heterogeneity of this architecture inevitably brings resource contention and energy shortage. In this work, we first study the impact of different capacity of router buffers on communication delay and energy consumption. After comprehensive evaluation with a spectrum of benchmarks with different characteristics, we reveal the implicit tradeoff between performance and energy consumption under different constrains of buffer resource. We further show that intelligently allocating more on-chip network buffer resources to compute-intensive nodes can significantly improve system performance. We introduce a runtime strategy that dynamically allocates network buffers to applications based on application characteristics. Our evaluation shows that our system reduces the communication delay by 55.47% on average, and reduces energy consumption of the system by 21% on average.

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Exploration on Routing Configuration of HNoC With Intelligent On-Chip Resource Management

Error injection has become critically important for testing the reliability of the hardware of any system. Measuring how a design under test reacts to different error injection methodologies is very essential for verification engineers to design dependable Universal Verification Methodology (UVM) scoreboards for error-detection purposes. The main target of this paper is to decide on the feasibility and compatibility of some error injection techniques when used with Networks-on-Chip (NoC) platforms. We target a UVM-based error injection and detection environment with its reusable components. Proposed techniques, introducing both positive and negative test scenarios, are applied to two example NoC components: a base router, which is a simple case study to prove proposed schemes and a configurable router, which is a complex open-source case study that provides the ability of changing the router's architecture with the change of some parameters and applied algorithms. The main novelty of our work is to integrate a full UVM environment with the various approaches of error injection and detection using reusable, generic UVM environment and components for NoC while inspecting network response according to error type and injection methodology.

On Error Injection for NoC Platforms: A UVM-based Practical Case Study

Fast routing verification with complexity effect for SOC

Emulation and verification framework for MPSoC based on NoC and RISC-V

In contrast to past projections using conventional bus-based interconnections, the use of Network on Chip (NoC) as an interconnection platform has become more promising to solve complex on-chip communication problems due to what it offers from scalability, reusability and efficiency. Moreover, providing a suitable test base to inspect and verify functionality of any IP core is a compulsory stage. To elaborate; Universal Verification Methodology (UVM) is introduced as a standardized and reusable methodology for verifying integrated circuit designs. In this paper, we present an architecture of a complete UVM environment to test generic routers through various test cases providing different scenarios to be applied. We also aim to establish a base on which other researchers can build to proceed towards finding better solutions.

A narrative of UVM testbench environment for interconnection routers: A practical approach

On-chip communication is one of the main challenges introduced to high level integrated system-on-chip design To address complexity and wiring challenges, network-on-chip has been proposed as a prominent solution capable of providing a reliable and efficient communication platform Accordingly, network design counts as a key parameter that defines the overall system performance In this paper, we propose a network design that integrates centralized routers in distributed networks Our results are compared to distributed networks of different sizes using a variety of synthetic traffic patterns and benchmarks

Performance evaluation of virtual channel flow control in centralized and distributed networks for system on chip

Significant increase in design complexity has triggered the need for the reusability of verification environments across different platforms including digital simulators, hardware emulators, and FPGA prototyping systems. In this paper, we propose a reusable testbench verification environment using Universal Verification Methodology applied to SystemC language (UVM-SystemC) that can be deployed with Design-under-Tests (DUTs) between different simulators, hardware emulators, and FPGA prototyping systems without changing the source code. Two case studies, Advanced Encryption Standard (AES) core and, Network on Chip (NoC) mesh, are introduced and tested using proposed verification environments and industrial functional verification tools.

Essraa Massoud

Papers

A narrative of UVM testbench environment for interconnection routers: A practical approach

Performance evaluation of virtual channel flow control in centralized and distributed networks for system on chip

A Reusable UVM-SystemC Verification Environment for Simulation, Hardware Emulation, and FPGA Prototyping: Case Studies