Field-programmable gate arrays (FPGAs) provide a significantly cheaper solution for various applications in traditional semiconductor electronics. Single flux quantum (SFQ) technologies are developing rapidly and the availability of SFQ-specific FPGA will be very useful. Towards developing such an SFQ-specific FPGA, new designs of FPGA subcircuits for both synchronous and asynchronous operation of SFQ circuits are presented in this paper. Magnetic Josephson junctions (MJJs) are used as bias limiting junctions in energy-efficient rapid SFQ (ERSFQ) biasing to implement programmable switches in various subcircuits of the proposed FPGA fabric. Designs of all FPGA subcircuits are developed and are verified through circuit simulation. Verilog hardware description language (HDL) models are also developed for all FPGA circuit blocks to facilitate large-scale FPGA simulations for the implementation of the desired circuit on the proposed FPGA fabric. Designs of a few subcircuits with switches based on nondestructive readout cell are also given in the current paper for better comparison with MJJ switch based counterparts. Programming of MJJ-based switches is based on the ability to control the critical current of MJJs externally. Recent implementations of SFQ decoder is proposed for accessing individual MJJs through the current lines in a crossbar structure. Estimations for the area and power consumption are much better in comparison to previous attempts at designing an SFQ specific FPGA.

Superconducting Magnetic Field Programmable Gate Array

A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

Logic drive based on standardized commodity programmable logic semiconductor IC chips

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells

A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.

Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells

Configuration values for Lookup tables (LUTs) and programmable routing switches in an FPGA are provided by means of a number of flip flops arranged in a shift register. This shift register may receive test values in a factory test mode, and operational configuration values (implementing whatever functionality the client requires of the FPGA) in an operational mode. The bitstreams are provided at one end of the shift register, and clocked through until the last flip flop receives its value. Values may also be clocked out at the other end of the shift register to be compared to the initial bitstream in order to identify corruption of stored values e.g. due to radiation exposure. A clock gating architecture is proposed for loading data to or reading data from specific selected shift registers.

System and method for testing and configuration of an fpga

FIELD: programmable logic devices.SUBSTANCE: user programmable gate array (FPGA) configured to implement a logic function, wherein the FPGA comprises a plurality of hardware search tables (LUT), wherein the selection lines or outputs of each LUT are programmable in a mutually connected manner to selection or output lines of another LUT through a plurality of programmable switches, multiple flip-flops in the shift register configuration, wherein each LUT has at least one input connected to the corresponding flip-flop output, and each programmable switch is connected to the additional corresponding trigger output; wherein FPGA is configured to operate in first mode, in which shift register is loaded with predetermined test values, and in second mode, in which shift register is loaded with values realizing said logic function.EFFECT: technical result is reduced space of chip allocated for addressing of cells of storage devices, improved testing.15 cl, 13 dwg

System and method of testing and configuring fpga

A multiple tiered programming structure (38, 41, 37) is provided for the memory cells determining the operation of a FPGA, where a first tier (38) comprising a set of program storage elements (3801-3814), possibly configured in a shift register is loaded with the program, whereby each program storage element passes its value on to a respective coupling device (41, 37) (which may also be a flip flop). The coupling devices are then clocked in synchrony (402, 412) to provide the values to the memory cells. This makes it possible to easily refresh the memory cells. In some embodiments a plurality of sets of coupling devices (37, 41) may be provided, and the memory cell can be loaded with the value from a selected one (3801-3814) of these coupling devices, or indeed directly from the set of program storage elements s. A mechanism (fig. 5: 39) may be provided for reading back from the coupling devices (fig. 5: 37) into the shift register (fig. 5: 38) so as to read out the values (fig. 5: output of Mux3901-3914) of the coupling devices for validation of the FPGA results.

Eydoux Julien

Papers

System and method for testing and configuration of an fpga

System and method of testing and configuring fpga

Fpga and method of fpga programming