Patent
System and method for testing and configuration of an fpga
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TLDR
In this article, a clock gating architecture is proposed for loading data to or reading data from specific selected shift registers, where bitstreams are provided at one end of the shift register, and clocked through until the last flip flop receives its value.Abstract:
Configuration values for Lookup tables (LUTs) and programmable routing switches in an FPGA are provided by means of a number of flip flops arranged in a shift register. This shift register may receive test values in a factory test mode, and operational configuration values (implementing whatever functionality the client requires of the FPGA) in an operational mode. The bitstreams are provided at one end of the shift register, and clocked through until the last flip flop receives its value. Values may also be clocked out at the other end of the shift register to be compared to the initial bitstream in order to identify corruption of stored values e.g. due to radiation exposure. A clock gating architecture is proposed for loading data to or reading data from specific selected shift registers.read more
Citations
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Journal ArticleDOI
Superconducting Magnetic Field Programmable Gate Array
TL;DR: New designs of FPGA subcircuits for both synchronous and asynchronous operation of SFQ circuits are presented in this paper, andEstimations for the area and power consumption are much better in comparison to previous attempts at designing an SFQ specific FPGAs.
Patent
Logic drive based on standardized commodity programmable logic semiconductor IC chips
Jin-Yuan Lee,Mou-Shiung Lin +1 more
TL;DR: A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate and an insulating dielectric layer between the first and second interconnection metal layers as mentioned in this paper.
Patent
Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
Jin-Yuan Lee,Mou-Shiung Lin +1 more
TL;DR: In this article, a look-up table (LUT) based logic function based on a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip is presented.
Patent
Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
Jin-Yuan Lee,Mou-Shiung Lin +1 more
TL;DR: In this paper, a look-up table is provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the PLC is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting value respectively.
Patent
Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
Jin-Yuan Lee,Mou-Shiung Lin +1 more
TL;DR: In this article, the first nonvolatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip.
References
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Patent
Linearization of a transmit amplifier
TL;DR: In this paper, a pre-distortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital to frequency converter (DFC), DPA and PA.
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Beebe Wayne Kevin,Botala Sally,Scott Whitney Gould,Frank Ray Keyser,Larsen Wendell Ray,Palmer Ronald Raymond,Brian A. Worth +6 more
TL;DR: In this paper, a programmable gate array includes test subsystems for testing various functional subsystems of the PAG array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.
Patent
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Patent
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TL;DR: In this article, configurable interconnect resources of field programmable gate arrays (FPGA's) are tested by configuring at least some of the lookup tables (LUT's), registers and input signal acquirers to implement one or more sequential state machines that feed back their current states via the interconnect conductors to the inputs of the LUT's.