This paper presents a dependence graph (DG) to visualize and describe a merged multiply-accumulate (MAC) hardware that is based on the modified Booth algorithm (MBA). The carry-save technique is used in the Booth encoder, the Booth multiplier, and the accumulator sections to ensure the fastest possible implementation. The DG applies to any MAC data word size and allows designing multiplier structures that are regular and have minimal delay, sign-bit extensions, and datapath width. Using the DG, a fast pipelined implementation is proposed, in which an accurate delay model for deep submicron CMOS technology is used. The delay model describes multi-level gate delays, taking into account input ramp and output loading. Based on the delay model, the proposed pipelined parallel MAC design is three times faster than other parallel MAC schemes that are based on the MBA. The speedup resulted from merging the accumulate and the multiply operations and the wide use of carry-save techniques.

A fast parallel multiplier-accumulator using the modified Booth algorithm

In this paper, we propose a new architecture of multiplier-and-accumulator (MAC) for high speed multiplication and accumulation arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator which has the largest delay in MAC was removed and its function was included into CSA, the overall performance becomes to be elevated. The proposed CSA tree uses 1's complement-based radix-2 modified booth algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of operands. The CSA propagates the carries by the least significant bits of the partial products and generates the least significant bits in advance for decreasing the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits not the output of the final adder for improving the performance by optimizing the efficiency of pipeline scheme. The proposed architecture was synthesized with and 90nm standard CMOS library after designing it. We analyzed the results such as hardware resource, delay, and pipeline which are based on the theoretical and experimental estimation. We used Sakurai's alpha power low for the delay modeling. The proposed MAC has the superior properties to the standard design in many ways and its performance is twice as much than the previous research in the similar clock frequency.

New VLSI Architecture of Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm

In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1's-complement-based radix-2 modified Booth's algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The CSA propagates the carries to the least significant bits of the partial products and generates the least significant bits in advance to decrease the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits instead of the output of the final adder, which made it possible to optimize the pipeline scheme to improve the performance. The proposed architecture was synthesized with 250, 180 and 130 ?m, and 90 nm standard CMOS library. Based on the theoretical and experimental estimation, we analyzed the results such as the amount of hardware resources, delay, and pipelining scheme. We used Sakurai's alpha power law for the delay modeling. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.

A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm

A method, apparatus and system for a scalable high capacity switch architecture involves a switching controller for use with a plurality of switching controllers in a switching system. Each switching controller has provisions for receiving a data packet, provisions for determining a destination of the data packet, provisions for determining whether any other switching controller in the system intends to transmit to the determined destination of the data packet and provisions for transmitting the received data packet to the determined destination when no other switching controllers intend to transmit to the determined destination.

Scalable high capacity switch architecture method, apparatus and system

This paper investigates the subcarrier and power allocation problem for an OFDM-based multiuser cognitive radio (CR) system. For CR systems it is important to keep the interference introduced to the primary user (PU) band within a tolerable range. Since the joint subcarrier and power allocation problem is a non-convex integer problem and a closed form solution is difficult to find, a suboptimal algorithm that separates subcarrier and power allocation is proposed. First, a suboptimal subcarrier algorithm is proposed that allocates subcarriers to CR users that not only increase the capacity, but also reduces the interference introduced to the primary user (PU) band. Further, for a given subcarrier allocation an optimal power loading algorithm is proposed that maximizes the capacity of CR users while keeping the interference introduced to the PU band and the total power below a threshold. Simulation results show that for CR systems the proposed algorithm is able to load power into the subcarriers while keeping the interference below a specified threshold.

/pdf/subcarrier-and-power-adaptation-for-multiuser-ofdm-based-dwuxswfrk9.pdf

Subcarrier and power adaptation for multiuser OFDM-based cognitive radio systems

Implementations for two-dimensional recursive filters using systolic arrays with linear structures are presented. The processing elements used are modular and thus lead to cost-effective designs. The implementations have the maximum data rate possible, i.e. a new input sample is supplied and as new output sample is obtained every sampling period. The latency of all the systolic arrays designed is equal to one. The number of processing elements required is on the order of w*h, where w and h are, respectively, the width and height of the window used. >

Systolic implementations of two-dimensional recursive digital filters

For testable design purposes, a multiple-output digital system needs a multiple-input signature register. This register accelerates the testing task by compressing multiple-input data streams into one signature. Existing designs depend on parallel feeding the input polynomials to the storage elements. These designs, give a good compression but, suffer from some drawbacks. The paper proposes a new design for the multiple-input signature register. This proposed design aggregates all inputs at a certain point and feeds them to the shift register. By adopting this concept, we are able to improve the operation of the multiple-input signature register in a number of ways. Complete VHDL modeling and simulation for the existing and the proposed designs verified the advantages of the new structure.

Multiple-input signature registers: an improved design

An iterative algorithm presented by Lim, Yang, and Koh (see IEEE Trans. Signal Processing, vol.41, p.1780-1789, 1993) is extended for the design of cosine-modulated pseudo-filter banks. The algorithm is simple, efficient, and results in savings in the amount of computation and design time. Design examples are included to illustrate the method.

http://ieeexplore.ieee.org/iel3/3913/11343/00519550.pdf

Efficient design of cosine-modulated filter banks

In this paper, a novel technique for the design of a high-speed word-level two's complement fixed-point inner-product processor is described. The new scheme offers a highly regular structure ideally suited for VLSI implementation. A comparison in terms of speed and area between the proposed scheme and two other inner-product processors is presented. A reduction in the computation time ranging from 20% to 50% compared with other schemes has been achieved using the proposed processor, without a significant increase in the required area.

https://ieeexplore.ieee.org/iel7/9754/6452208/06591122.pdf

High-speed area-efficient inner-product processor

Several DSP applications demand high speed inner-product processors (IPP). Most current implementations of IPP use the multiply-accumulate (MAC) concept to perform the IP operations. Rather than using MAC accumulate to perform the IP operation, the authors show two superior designs, MIPP and CSIPP, that outperform the standard implementations. The speed improvement ratio is estimated to be between 2 to 4 for both designs. The paper also presents a new technique to detect and correct overflow occurrence in MIPP and CSIPP.

F. El-Guibaly

Papers

Systolic implementations of two-dimensional recursive digital filters

Multiple-input signature registers: an improved design

Efficient design of cosine-modulated filter banks

High-speed area-efficient inner-product processor

Overflow handling in inner-product processors