Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them allows fast design time, ease of routing, predictability of electrical parameters and good scalability. k-ary n-mesh topologies are candidate solutions for these systems, borrowed from the domain of off-chip interconnection networks. However, the on-chip integration has to deal with unique challenges at different levels of abstraction. From a technology viewpoint, interconnect reverse scaling causes critical paths to go across global links. Poor interconnect performance might also impact IP core speed depending on the synchronization mechanism at the interface. Finally, this might also conflict with the requirements that communication libraries employed in the MPSoC domain pose on the underlying interconnect fabric. This paper provides a comprehensive overview of these topics, by characterizing physical feasibility of representative k-ary n-mesh topologies and by providing silicon-aware system-level performance figures.

Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints

In this study, we address the increased computational demands of a frequency-diverse ultrasonic target detection system by developing a zero-phase IIR (ZP-IIR) filter. Several ZP-IIR filter types including Chebyshev-I, Chebyshev- II, and Butterworth were analyzed for their detection performance. The 4th-order filters with 8-bit quantized coefficients are shown to improve the flaw-to-clutter ratio by approximately 10 dB. Furthermore, the reduced adder graph algorithm is used for a hardware realization of ZP-IIR filters that does not require any dedicated multipliers. A small number of coefficients inherent to IIR filters and their multiplierless implementation provide efficient architecture suitable for compact, real-time ultrasonic imaging devices.

Hardware-efficient realization of a real-time ultrasonic target detection system using IIR filters

In the implementation process of a convolution neural network (CNN)-based object detection system, the primary issues are power dissipation and limited throughput. Even though we utilize ultra-low power dissipation devices, the dynamic power dissipation issue will be difficult to resolve. During the operation of the CNN algorithm, there are several factors such as the heating problem generated from the massive computational complexity, the bottleneck generated in data transformation and by the limited bandwidth, and the power dissipation generated from redundant data access. This article proposes the low-power techniques, applies them to the CNN accelerator on the FPGA and ASIC design flow, and evaluates them on the Xilinx ZCU-102 FPGA SoC hardware platform and 45 nm technology for ASIC, respectively. Our proposed low-power techniques are applied at the register-transfer-level (RT-level), targeting FPGA and ASIC. In this article, we achieve up to a 53.21% power reduction in the ASIC implementation and saved 32.72% of the dynamic power dissipation in the FPGA implementation. This shows that our RTL low-power schemes have a powerful possibility of dynamic power reduction when applied to the FPGA design flow and ASIC design flow for the implementation of the CNN-based object detection system.

https://www.mdpi.com/2079-9292/9/3/478/pdf

Low-Power RTL Code Generation for Advanced CNN Algorithms toward Object Detection in Autonomous Vehicles

In this study, we address the increased computational demands of a frequency-diverse ultrasonic target detection system by developing a zero-phase IIR (ZP-IIR) filter. Several ZP-IIR filter types including Chebyshev-I, Chebyshev-II, and Butterworth were analyzed for their detection performance. The 4th-order filters with 8-bit quantized coefficients are shown to improve the flaw-to-clutter ratio by approximately 10 dB. Furthermore, the reduced adder graph algorithm is used for a hardware realization of ZP-IIR filters that does not require any dedicated multipliers. A small number of coef f icients inherent to IIR filters and their multiplierless implementation provide efficient architecture suitable for compact, real-time ultrasonic imaging devices.

Hardware-Efficient Realization of a Real-Time Ultrasonic Target Detection System Using IIR Filters

Afin de repondre a une complexite croissante des systemes de calcul, due notamment aux progres rapides et permanents des technologies de l'information, de nouveaux paradigmes et solutions architecturales basees sur des structures auto-adaptatives, auto-organisees sont a elaborer. Ces dernieres doivent permettre d'une part la mise a disposition d'une puissance de calcul suffisante repondant a des contraintes de temps severes (traitement temps reel). D'autre part, de disposer d'une grande flexibilite et adaptabilite dans le but de repondre aux evolutions des traitements ou des defaillances non prevues caracterisant un contexte d'environnement evolutif de fonctionnement du systeme. C'est dans ce cadre que s'inserent les travaux de recherche presentes dans cette these qui consistent a developper une architecture auto-organisee de type Reconfigurable MPSoC (Multi processor System on Chip) a base de technologie FPGA.

/pdf/architecture-reconfigurable-de-systeme-embarque-auto-2dczrebn4s.pdf

Architecture reconfigurable de système embarqué auto-organisé

The objective of this work is to design and implement an Image and Video Processing Platform (IVPP) on FGPAs using PICO based HLS. This hardware/software codesign platform has been implemented on a Xilinx Virtex-5 FPGA. The video interface blocks are done in RTL and the initialization phase is done using a MicroBlaze processor allowing the support of multiple video resolutions. This paper discusses the architectural building blocks showing the flexibility of the proposed platform. This flexibility is achieved by using a new design flow based on PICO. IVPP allows custom-processing blocks to be plugged-in to the platform architecture without modifying the front-end (capturing video data) and back-end (displaying processed output). This paper presents several examples of video processing applications, such as a Canny edge detector, motion detector and object tracking that have been realized using IVPP for real-time video processing.

HW/SW co-design platform for image and video processing applications on Virtex-5 FPGA using PICO

Network on a chip (NoC) topologies for interconnect offer the possibility of increasing the flexibility and performance of an embedded computational platform. NoC is also an enabling factor for the creation of dynamically reconfigurable single chip systems. In this paper, the NOVA interconnect topology is shown. NOVA is a hybrid topology for NoC interconnect targeted at an FPGA. This topology is able to efficiently support the communication workloads associated with multiprocessor, multi peripheral and reconfigurable systems. This paper presents simulation results on the performance and scalability of NOVA. Also, the performance of NOVA is compared to the star, torus, and hypercube topologies, and is shown to outperform these topologies.

NOVA interconnect for dynamically reconfigurable NoC systems

In this study, we address the increased computational demands of real-time ultrasonic data processing by developing an efficient frequency-diverse detection algorithm and architecture. Substantial computational savings can be obtained if the FIR filters utilized in frequency-diverse detection methods are replaced by IIR (infinite impulse response) filters. IIR filter implementations involve a much lower number of coefficients with similar filtering characteristics. However, the design of IIR filters results in phase distortion which shifts the frequency dependant signal features. This drawback greatly deteriorates the detection performance of the designed IIR bandpass filters. Consequently, for protection against phase distortion, an IIR zero-phase filter has been designed and presented. In this study, Reduced Adder Graph (RAG) algorithm is used for a hardware realization of IIR filters that does not require any dedicated multipliers. A small number of coefficients inherent to IIR filters and their multiplierless implementation provide an optimal architecture suitable for real-time ultrasonic imaging applications.

F. Martinez Vallina

Papers

HW/SW co-design platform for image and video processing applications on Virtex-5 FPGA using PICO

NOVA interconnect for dynamically reconfigurable NoC systems

Efficient hardware realization of frequency-diverse ultrasonic flaw detection using zero-phase IIR filters