ALICE (A Large Ion Collider Experiment) is a general-purpose, heavy-ion detector at the CERN LHC which focuses on QCD, the strong-interaction sector of the Standard Model. It is designed to address the physics of strongly interacting matter and the quark-gluon plasma at extreme values of energy density and temperature in nucleus-nucleus collisions. Besides running with Pb ions, the physics programme includes collisions with lighter ions, lower energy running and dedicated proton-nucleus runs. ALICE will also take data with proton beams at the top LHC energy to collect reference data for the heavy-ion programme and to address several QCD topics for which ALICE is complementary to the other LHC detectors. The ALICE detector has been built by a collaboration including currently over 1000 physicists and engineers from 105 Institutes in 30 countries. Its overall dimensions are 161626 m3 with a total weight of approximately 10 000 t. The experiment consists of 18 different detector systems each with its own specific technology choice and design constraints, driven both by the physics requirements and the experimental conditions expected at LHC. The most stringent design constraint is to cope with the extreme particle multiplicity anticipated in central Pb-Pb collisions. The different subsystems were optimized to provide high-momentum resolution as well as excellent Particle Identification (PID) over a broad range in momentum, up to the highest multiplicities predicted for LHC. This will allow for comprehensive studies of hadrons, electrons, muons, and photons produced in the collision of heavy nuclei. Most detector systems are scheduled to be installed and ready for data taking by mid-2008 when the LHC is scheduled to start operation, with the exception of parts of the Photon Spectrometer (PHOS), Transition Radiation Detector (TRD) and Electro Magnetic Calorimeter (EMCal). These detectors will be completed for the high-luminosity ion run expected in 2010. This paper describes in detail the detector components as installed for the first data taking in the summer of 2008.

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The ALICE experiment at the CERN LHC

A low noise transimpedance amplifier (TIA) is used in radiation detectors to transform the current pulse produced by a photo-sensitive device into an output voltage pulse with a specified amplitude and shape. We consider here the specifications of a PET (positron emission tomography) system. We review the traditional approach, feedback TIA, using an operational amplifier with feedback, and we investigate two alternative circuits: the common-gate TIA, and the regulated cascode TIA. We derive the transimpedance function (the poles of which determine the pulse shaping); we identify the transistor in each circuit that has the dominant noise source, and we obtain closed-form equations for the rms output noise voltage. We find that the common-gate TIA has high noise, but the regulated cascode TIA has the same dominant noise contribution as the feedback TIA, if the same maximum transconductance value is considered. A circuit prototype of a regulated cascode TIA is designed in a 0.35 μm CMOS technology, to validate the theoretical results by simulation and by measurement.

Noise Performance of a Regulated Cascode Transimpedance Amplifier for Radiation Detectors

A transimpedance amplifier (TIA) in the front-end of a radiation detector is required to convert the current pulse produced by a light-detector to a voltage pulse with amplitude and shape suitable for the subsequent processing. We consider in this paper the specifications of a positron emission tomography (PET) scanner for medical imaging. The conventional approach is to use an avalanche photo-diode (APD) as the light-detector and a feedback TIA. We point out here that, when the APD is replaced by the more recent silicon photomultiplier (SiPM), a feedback TIA is not suitable, and we propose the use of a regulated common-gate (RC-G) TIA. We derive the transimpedance function of the RC-G TIA considering the parasitic capacitances that have a dominant effect on the pulse shaping. We use the result obtained to establish TIA design guidelines, and we show that these should be different with an APD and with a SiPM at the input. We identify the dominant noise source in the RC-G TIA, and we derive a closed form equation for the output noise rms voltage. A prototype TIA was designed for UMC 130 nm CMOS technology. We present simulation and experimental results that confirm that the RC-G circuit is suitable for implementation of the TIAs in the front-end of a PET scanner using SiPMs at the input.

Regulated Common-Gate Transimpedance Amplifier Designed to Operate With a Silicon Photo-Multiplier at the Input

The state of analog-to-digital converters (ADCs) is surveyed and summarized for 150 ADCs simultaneously possessing sample rates greater than or equal to one Megasample/second (2 1 Msps), and bit resolutions greater than or equal to twelve bits (2 12-bits). These performance metrics are commonly specified for defense space applications. Converter performance results are presented with respect to bit resolution, sample rate, power dissipation, and spurious-free dynamic range (SFDR). A performance comparison is made between ADCs produced fiom commercial versus research and development (R&D) sources. The state of semiconductor process technology for M C s is summarized in terms of power supply voltage, substrate technology, and minimum process geometry. Results showed no fundamental limitation in powedspeed performance in high performance pipeline ADCs as CMOS processes are scaled into deep submicron (0.25 pm) geometries, and analog voltage supplies are scaled down to 3.0 V. The pipeline architecture is demonstrated as pervasive within this performance specification range. Results demonstrate commercially available ADCs generally do not meet basic performance specifications or radiation hardness requirements for defense space missions. Recommendations are presented for development of ADCs in scaled, silicon-based process technologies such as SiGe BiCMOS coupled with hardened by design techniques. The survey serves as a tool for assessing the current state of ADC development and for determining future target goals for M C performance. TABLE OF CONTENTS

A survey of high performance analog-to-digital converters for defense space applications

With the construction of the Large Hadron Collider at the European Center for Nuclear Research (CERN), the radiation levels at large High Energy Physics (HEP) experiments are significantly increased with respect to past experience. The approach the HEP community is using to ensure radiation tolerance of the electronics installed in these new generation experiments is described. Particular attention is devoted to developments that led to original work: the estimate of the SEU rate in the complex LHC radiation environment and the use of hardness by design techniques to achieve radiation hardness of ASICs in a commercial CMOS technology.

Radiation issues in the new generation of high energy physics experiments

This paper presents the design and test of a low power analog-to-digital converter (ADC) implemented in a commercial 0.25 /spl mu/m CMOS technology. The circuit has been developed to serve as a building block in multichannel data acquisition systems for high energy physics (HEP) applications. Therefore, medium resolution (10 bits), very low power consumption, and high modularity are the key features of the design. In HEP experiments, the resistance of the electronics to the ionizing radiation is often a primary issue. Hence, the ADC has been laid out using a radiation-tolerant approach. The test results show that the chip operates as a full 10-bit converter up to a clock frequency of 30 MHz. No degradation in performance has been measured after a total dose of 10 Mrd (SiO/sub 2/).

A low-power 10 bit ADC in a 0.25 /spl mu/m CMOS: design considerations and test results

In this paper we present a 32 channel ASIC prototype for the readout of the Silicon Drift Detectors (SDDs) of the ALICE experiment. The ASIC integrates on the same chip 32 transimpedance amplifiers, a 32/spl times/256 cells analogue memory and 16 successive approximation 10 bit A/D converters. The circuit amplifies and samples at 40 MS/s the input signal in a continuous way; when an external trigger signal validates the acquisition, the sampling is stopped and the data are digitized at lower speed (0.5 MS/s). The chip has been designed and fabricated in a commercial. 0.25/spl mu/m CMOS technology. It has been extensively tested both on a bench and connected with the detector in several beam tests. In this paper both design issues and test results are presented. The commercial technology used for the design has been yield radiation tolerant with special layout techniques. Total dose irradiation tests are also presented.

F. Rotondo

Papers

A low-power 10 bit ADC in a 0.25 /spl mu/m CMOS: design considerations and test results

A 32-channels, 0.25 /spl mu/m CMOS ASIC for the readout of the Silicon Drift Detectors of the ALICE experiment