The purpose of this paper is to present a systematic survey of the theoretical/experimental work accomplished in the area of digital phase-locked loops (DPLL's) during the period of 1960 to 1980. The DPLL represents the heart of the Building blocks required in the implementation of coherent (all digital) communications and tracking receivers. This survey is particularly motivated by the fact that microprocessor technology is advancing rapidly to the extent that sophisticated and flexible signal processing algorithms for communications and control can be realized in the digital domain. In fact, it is anticipated that the use of this signal processing technology will continue to expand rapidly in the development of advanced communications and tracking receivers, e.g., all digital modems. Consequently, one major purpose of this paper is to provide the reader with a survey and an overview of the theoretical and experimental work accomplished to date, thereby offering speedy access to the techniques and hardware developments which have been presented in a scattered literature. In addition, the authors feel that a tutorial article revealing the various theories, their relationships to one another, their shortcomings, their advantages and the assumptions on which each is based, would be of tremendous value to the engineer trying to decide what particular analysis procedure is applicable to his peculiar problem. Consequently, a byproduct of this presentation will be to point out unsolved problems of practical interest. A broad class of digital modulation techniques, viz. I-Q modulations and demodulation, are studied in a rather general way.

A survey of digital phase-locked loops

In this paper, a nonuniform-sampling digital phaselocked loop (DPLL) called the digital tanlock loop (DTL), which uses a new type of phase error detector with linear phase characteristic, is studied. The main feature of the DTL is that the phase error detector, using the tan^{-1}(.) function with in-phase and quadrature samples of the incoming signal, has a linear characteristic with a period of 2π. Accordingly, the DTL can be characterized by a linear difference equation, thereby making it possible to analyze the loop easily, without approximation of nonlinearity as is usually done in analysis of a conventional DPLL with sinusoidal phase characteristic. The performances of the first- and second-order DTL's in the absence and presence of noise have been investigated by analysis and computer simulation. It is shown that the linear phase characteristic results in many attractive features in comparison to the conventional DPLL with the sinusoidal phase characteristic. These include insensitivity of the locking conditions to variation of input signal power, more noise immunity, wider lock range and less steady-state phase error of the first-order loop for an input with frequency offset, and much less sensitivity to initial phase errors in convergence of the second-order loop.

Performance Analysis of Digital Tanlock Loop

The behavior of a digital phase-locked loop (DPLL) which tracks the positive-going zero crossings of the incoming signal can be characterized by a nonlinear difference equation in the phaseerror process. This equation was first presented by Gill and Gupta for the CW loop, and modified by Osborne and Lindsey for the N th power loop. Stability results have been previously obtained for first- and second-order loops by linearizing the equation about the steady-state solution. However, in this paper, a mathematically more rigorous and powerful approach is introduced whereby the acquisition behavior is studied by formulating the equation as a fixed-point problem. Stability results can be obtained by studying the nonlinear equation directly, using theorems pertaining to the convergence behavior of the Picard iterates, e.g., Ostrowski's Theorem and the Contraction Mapping Theorem. Using this formulation, we present some new stability results (and rederive some previously obtained results) for the first- and second-order DPLL's. Then, some stability results for the third-order DPLL are derived for the first time. The first-order DPLL results appear in Part I, and the higher order DPLL results appear in Part II.

Stability Analysis of an Nth Power Digital Phase-Locked Loop--Part I: First-Order DPLL

A Short Survey of Frequency Synthesizer Techniques

Recent work on the subject of digital phase-locked loops (DPLL's) has examined the unwanted phase jitter that occurs in such systems due to frequency quantization in a number-controlled oscillator. In this paper, we show that the theory of nonlinear dynamics can provide an analytical explanation of this phase jitter, along with other features of the system behavior. In particular, we will describe the phase-jitter dynamics mathematically in terms of the well-known circle rotation map and area-preserving twist map.

http://ieeexplore.ieee.org/iel5/81/16530/00762920.pdf

Phase-jitter dynamics of digital phase-locked loops

A non-uniform sampling digital phase locked loop (DPLL), with a hard limiter as quantizer, is analyzed by a graphical method in the case of phase and frequency step inputs and no noise. The cycle slipping and the limit cycles phenomena are investigated. An upper-bound to the model gain and, consequently, to the pull-in range is obtained. Also a closed-form expression of acquisition time is derived. Moreover, using a random-walk model, the stationary phase error variance, the mean acquisition time and the mean first slip time have been evaluated. Some two channel configurations are proposed, which allow us to obtain a faster acquisition. Finally the problems relevant to the practical implementation of the loop are analyzed.

F. Russo

Papers

A Binary Quantized Digital Phase Locked Loop: A Graphical Analysis