Journal ArticleDOI
A Binary Quantized Digital Phase Locked Loop: A Graphical Analysis
N. D'Andrea,F. Russo +1 more
TLDR
A non-uniform sampling digital phase locked loop (DPLL), with a hard limiter as quantizer, is analyzed by a graphical method in the case of phase and frequency step inputs and no noise and an upper-bound to the model gain and to the pull-in range is obtained.Abstract:
A non-uniform sampling digital phase locked loop (DPLL), with a hard limiter as quantizer, is analyzed by a graphical method in the case of phase and frequency step inputs and no noise. The cycle slipping and the limit cycles phenomena are investigated. An upper-bound to the model gain and, consequently, to the pull-in range is obtained. Also a closed-form expression of acquisition time is derived. Moreover, using a random-walk model, the stationary phase error variance, the mean acquisition time and the mean first slip time have been evaluated. Some two channel configurations are proposed, which allow us to obtain a faster acquisition. Finally the problems relevant to the practical implementation of the loop are analyzed.read more
Citations
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Journal ArticleDOI
A survey of digital phase-locked loops
William C. Lindsey,Chak Chie +1 more
TL;DR: A systematic survey of the theoretical/experimental work accomplished in the area of digital phase-locked loops (DPLL's) during the period of 1960 to 1980, thereby offering speedy access to the techniques and hardware developments which have been presented in a scattered literature.
Journal ArticleDOI
Performance Analysis of Digital Tanlock Loop
TL;DR: It is shown that the linear phase characteristic of the digital tanlock loop results in many attractive features in comparison to the conventional DPLL with the sinusoidal phase characteristic, including insensitivity of the locking conditions to variation of input signal power, more noise immunity, wider lock range and less steady-state phase error of the first-order loop for an input with frequency offset.
Journal ArticleDOI
Stability Analysis of an Nth Power Digital Phase-Locked Loop--Part I: First-Order DPLL
TL;DR: A mathematically more rigorous and powerful approach is introduced whereby the acquisition behavior is studied by formulating the equation as a fixed-point problem, and some stability results for the third-order DPLL are derived for the first time.
Journal ArticleDOI
Phase-jitter dynamics of digital phase-locked loops
TL;DR: In this paper, the authors describe the phase-jitter dynamics mathematically in terms of the well-known circle rotation map and area-preserving twist map and show that the theory of nonlinear dynamics can provide an analytical explanation of this phase jitter, along with other features of the system behavior.
References
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Journal ArticleDOI
Phase-locked loops
TL;DR: An attempt to systematically outline the work done in the area of phase-locked loops which are now used in modern communication system design is presented.
Journal ArticleDOI
First-Order Discrete Phase-Locked Loop with Applications to Demodulation of Angle-Modulated Carrier
G. Gill,S.C. Gupta +1 more
TL;DR: A first-order discrete phase-locked loop that tracks the phase of an incoming analog signal at discrete instants of time occurring once per cycle of the carrier is developed.
Journal ArticleDOI
Performance of a First-Order Transition Sampling Digital Phase-Locked Loop Using Random-Walk Models
TL;DR: A new mechanization of a first-order all digital phaselocked loop (ADPLL) is discussed and analyzed, and an upper bound on the timing-error bias due to a Doppler shift of the synchronized waveform is derived.
Journal ArticleDOI
On Higher Order Discrete Phase-Locked Loops
TL;DR: An exact mathematical model is developed for a discrete loop of a general order particularly suitable for digital computation and the model of the noisy loop is derived and the optimization of the loop filter for minimum mean-square error is considered.
Journal ArticleDOI
A Class of All Digital Phase Locked Loops: Modeling and Analysis
C. P. Reddy,Someshwar C. Gupta +1 more
TL;DR: An all digital phase locked loop which tracks the phase of the incoming signal once per carrier cycle is proposed and the lock range for the general model is derived.
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