An integrated design environment (IDE) is disclosed for forming virtual embedded systems The IDE includes a design language for forming finite state machine models of hardware components that are coupled to simulators of processor cores, preferably instruction set accurate simulators A software debugger interface permits a software application to be loaded and executed on the virtual embedded system A virtual test bench may be coupled to the simulation to serve as a human-machine interface In one embodiment, the IDE is provided as a web-based service for the evaluation, development and procurement phases of an embedded system project IP components, such as processor cores, may be evaluated using a virtual embedded system In one embodiment, a virtual embedded system is used as an executable specification for the procurement of a good or service related to an embedded system

Method and system for virtual prototyping

A method and system for co-verifying a hardware simulation of a field-programmable-system-level integrated circuit (FPSLIC) and a software simulation of the field-programmable-system-level integrated circuit A FPSLIC device is simulated in hardware, and a simulator-port layout of the FPSLIC device is generated In software, the method separately simulates, with an instruction-set simulator, the FPSLIC device, and outputs register contents from the instruction-set software The contents from the simulator-port layout are verified with the register contents Additionally, the method may further include outputting peripheral contents from the instruction-set simulator, and verifying contents from the simulator-port layout with the peripheral contents UART contents also may be outputted from the instruction-set simulator, and verified with contents from the simulator-port layout with the UART contents

Software tool to allow filed programmable system level devices

A storage medium is disclosed. The storage medium having stored on it a set of programming instructions defining a number of data objects and operations on the data objects for use by another set of programming instructions to enable the other set of programming instructions to be compilable into either a version suitable for use in a hardware/software co-simulation that effectively includes calls to hardware simulation functions that operate to generate bus cycles for a hardware simulator, or another version without the effective calls, but explicitly expressed instead, suitable for use on a targeted hardware.

Method and apparatus for generating co-simulation and production executables from a single source

A hardware/software co-simulation permits access to a server state from any process in the hardware/software co-simulation. In one embodiment, a co-simulation interface receives a request from a client system for configuration data for the server state in of the hardware/software co-simulation. The configuration data defines memory locations in the co-simulation from which the server state can be assembled. The interface inserts the request in the co-simulation. The co-simulation responds with the configuration information. Based on the configuration information, memory operations can be performed on the server state.

Accessing state information in a hardware/software co-simulation

A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted wherein, first, a timed software component described in a C-based language or constructed from binary code native to the host CPU and a hardware component described in the C-based language are input as verification models, necessary compiling is performed, and the compiled components are linked together. Next, a testbench is input and compiled. Then, the components and the testbench are linked together, after which simulation is performed and the result of the simulation is output.

Method for co-verifying hardware and software for a semiconductor device

We propose a top-down hardware/software co-simulation method for embedded systems and introduce a component logical bus architecture as an interface between software components and hardware components. Co-simulation using a component logical bus architecture is possible in the same environment from the stage at which the processor is not yet determined to the stage at which the processor is modeled in register transfer language. A model whose design is based on a component logical bus architecture is replaceable and reusable. By combining such replaceable models, it is possible to quickly realize seamless co-simulation. We further describe experimental results of our approach.

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F. Suzuki

Papers

A top-down hardware/software co-simulation method for embedded systems based upon a component logical bus architecture