Showing papers by "Fabrizio Lombardi published in 1994"
30 May 1994
TL;DR: This paper presents a new approach for finding the Unique Input/Output (UIO) sequences of the states in of a finite state machine (FSM), which utilizes a different data structure for organizing the search tree.
Abstract: This paper presents a new approach for finding the Unique Input/Output (UIO) sequences of the states in of a finite state machine (FSM). The proposed approach utilizes a different data structure for organizing the search tree. This reduces the amount of time and memory space required for finding the UIO sequences of all states of a FSM. Simulation results on sample benchmark FSMs from MCNC and commercially available protocols are provided. >
5 citations
31 Jan 1994
TL;DR: New improved methods for detecting latent sector faults in a disk subsystem as caused by media deterioration of the disk magnetic storage material and an adaptive algorithm is proposed to utilize the idle time of the disks for scanning commonly used SCSI disks.
Abstract: The authors present new improved methods for detecting latent sector faults in a disk subsystem as caused by media deterioration of the disk magnetic storage material. In case of media deterioration on the rarely accessed sectors, a latent disk fault may remain undetected for a long time. An adaptive algorithm is proposed to utilize the idle time of the disk for scanning commonly used SCSI disks. >
4 citations
17 Oct 1994
TL;DR: This paper presents analytical and simulation models for evaluating the operation of a VLSI processor (in a uniprocessor configuration) which utilizes a time-redundant approach (such as recomputation by shifted operands) for fault-tolerant computing.
Abstract: This paper presents analytical and simulation models for evaluating the operation of a VLSI processor (in a uniprocessor configuration) which utilizes a time-redundant approach (such as recomputation by shifted operands) for fault-tolerant computing. In the proposed approach, all incoming jobs to the uniprocessor are duplicated, thus two versions of each job must be processed. A discrepancy in the results produced by comparing the outcomes of the two versions of the same job indicates that a fault may have occurred. Several methods for appropriately scheduling the primary and secondary versions of the jobs are proposed and analyzed.
3 citations
19 Jan 1994
TL;DR: The proposed approach utilizes the augmented switching interconnection network (commonly found in reconfigurable arrays) as multiple parallel scan chains, such that controllability and observability of test vectors can be achieved for each cell.
Abstract: This paper presents a new approach for diagnosing (detection and location) reconfigurable two-dimensional arrays. The proposed approach utilizes the augmented switching interconnection network (commonly found in reconfigurable arrays) as multiple parallel scan chains, such that controllability and observability of test vectors can be achieved for each cell. Arrays with homogeneous and nonhomogeneous cells (multipipeline) are analyzed. An example of the application of the proposed approach to an existing array architecture for image processing, is presented. >
3 citations
19 Jan 1994
TL;DR: It is proved that an algorithm which maximizes the number of reconfigured pipelines (optimality) is possible in an execution complexity lower than a previous algorithm based on a maximum flow approach.
Abstract: This paper presents a new algorithm for reconfiguring WSI multipipeline arrays in the presence of faults in links, processing elements (PE's) and switching elements (SE's). Using a fault model in which a PE and link can be either fault free or faulty and a SE is modeled by relating its switching capabilities to its status and the status of the connecting links, it is proved that an algorithm which maximizes the number of reconfigured pipelines (optimality) is possible in an execution complexity lower than a previous algorithm based on a maximum flow approach. The proposed approach is based on a greedy algorithm with an execution complexity of O(n/spl times/m), where n is the number of stages (or columns) of the array and m is the number of PE's in a stage. >
2 citations
01 May 1994
TL;DR: It is proved that the proposed approach provides 100% fault coverage for a single nonredundant fault and requires a significant smaller number of phases than previous scan approaches.
Abstract: The paper presents a new approach for design-for-testability (DFT) of sequential circuits. The proposed approach is based on augmenting the system under test (SUT) which is modelled as a Mealy machine, with circuitry such that the combinational part of the SUT and the sequential part (i.e. The flip-flops can be tested independently (disjoint testing). A partial parallel scan method is used with a multiphase technique. Two extra input lines are required with no modification to the memory elements. It is proved that the proposed approach provides 100% fault coverage for a single nonredundant fault and requires a significant smaller number of phases than previous scan approaches. Simulation results shows that, for benchmark circuits, the proposed approach requires a significant lower number of tests than previous approaches. The area overhead for either a PLA or a two-level realisation of the combinational part of the SUT is very modest.
2 citations
TL;DR: A novel method for generating non-standard random distributions required when the system cannot be modelled accurately using conventional probabilistic distributions is introduced.
1 citations
15 Aug 1994
TL;DR: This paper presents a new approach for rank order filtering on a MasPar array architecture in the presence of faulty processors based on offseting the loss of one or more faulty processors using the available computational capacity of the neighbor fault-free processors.
Abstract: This paper presents a new approach for rank order filtering on a MasPar array architecture in the presence of faulty processors. This approach is based on offseting the loss of one or more faulty processors (due to either faults, or defects in the manufacturing process) using the available computational capacity of the neighbor fault-free processors. A parallel algorithm which is applicable to this fault-tolerant procedure, is proposed with a time complexity ofO(N), where N is the dimension of the array.
14 Dec 1994
TL;DR: Two parallel matrix multiplication algorithms are presented and their novelty is the utilization of communication schemes which theoretically are distance insensitive; the impact on the communication and computational complexities and costs compared with a theoretical analysis, is analyzed and evaluated.
Abstract: Two parallel matrix multiplication algorithms are presented in this paper. These algorithms execute on a grid with toroidal connections. Their novelty is the utilization of communication schemes which theoretically are distance insensitive; the impact on the communication and computational complexities and costs compared with a theoretical analysis, is analyzed and evaluated. The proposed algorithms have been implemented on a MasPar array. An experimental evaluation of these algorithms is performed. A comparison is made for matrix multiplication between the MasPar and the SUN-4/390. >
17 Oct 1994
TL;DR: This paper addressed the issue of cost for programming soft switches involved in the routing process for the interconnections from the primary pad pins in an augmented interconnection network of a two-dimensional VLSI/WSI array.
Abstract: This paper deals with the programming and control of non-permanent (soft) switching elements in an augmented interconnection network of a two-dimensional VLSI/WSI array. In particular, it is addressed the issue of cost for programming soft switches involved in the routing process for the interconnections from the primary pad pins. Cost is analyzed with respect to the complexity of the switches (as given by their switching modes) and the number of programming steps involved in establishing the desired interconnections.
26 Oct 1994
TL;DR: A divide-and-conquer methodology of fault diagnosis for a general class of processor arrays, which is one of the most popular architectures in today's multiprocessor systems, and an algorithm for 2D arrays is proposed.
Abstract: System-level diagnosis in a multiprocessor system should be both effective and efficient. Most of the existing results are not applicable in practice because of the high diagnosis cost and limited diagnosability. We propose a divide-and-conquer methodology of fault diagnosis for a general class of processor arrays, which is one of the most popular architectures in today's multiprocessor systems. Parallel testing and adaptive diagnosis are our major strategies. The over-d fault problem is inherently tackled through a deterministic method. Based on this unified methodology, we first propose an algorithm for 2D arrays. Moreover, our methodology can be fully explored to those multi-dimensional arrays with high degree of hierarchy like hypercubes. We thus propose another diagnosis algorithm for this kind of architectures. Analytical and simulation results show that our approaches are superior. >