An overview is presented of the current state-of-the-art in silicon nanophotonic ring resonators. Basic theory of ring resonators is discussed, and applied to the peculiarities of submicron silicon photonic wire waveguides: the small dimensions and tight bend radii, sensitivity to perturbations and the boundary conditions of the fabrication processes. Theory is compared to quantitative measurements. Finally, several of the more promising applications of silicon ring resonators are discussed: filters and optical delay lines, label-free biosensors, and active rings for efficient modulators and even light sources.

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Silicon microring resonators

Modern processors use branch prediction and speculative execution to maximize performance. For example, if the destination of a branch depends on a memory value that is in the process of being read, CPUs will try to guess the destination and attempt to execute ahead. When the memory value finally arrives, the CPU either discards or commits the speculative computation. Speculative logic is unfaithful in how it executes, can access the victim's memory and registers, and can perform operations with measurable side effects. Spectre attacks involve inducing a victim to speculatively perform operations that would not occur during correct program execution and which leak the victim's confidential information via a side channel to the adversary. This paper describes practical attacks that combine methodology from side channel attacks, fault attacks, and return-oriented programming that can read arbitrary memory from the victim's process. More broadly, the paper shows that speculative execution implementations violate the security assumptions underpinning numerous software security mechanisms, including operating system process separation, containerization, just-in-time (JIT) compilation, and countermeasures to cache timing and side-channel attacks. These attacks represent a serious threat to actual systems since vulnerable speculative execution capabilities are found in microprocessors from Intel, AMD, and ARM that are used in billions of devices. While makeshift processor-specific countermeasures are possible in some cases, sound solutions will require fixes to processor designs as well as updates to instruction set architectures (ISAs) to give hardware architects and software developers a common understanding as to what computation state CPU implementations are (and are not) permitted to leak.

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Spectre Attacks: Exploiting Speculative Execution

Intel’s Software Guard Extensions (SGX) is a set of extensions to the Intel architecture that aims to provide integrity and confidentiality guarantees to securitysensitive computation performed on a computer where all the privileged software (kernel, hypervisor, etc) is potentially malicious. This paper analyzes Intel SGX, based on the 3 papers [14, 78, 137] that introduced it, on the Intel Software Developer’s Manual [100] (which supersedes the SGX manuals [94, 98]), on an ISCA 2015 tutorial [102], and on two patents [108, 136]. We use the papers, reference manuals, and tutorial as primary data sources, and only draw on the patents to fill in missing information. This paper’s contributions are a summary of the Intel-specific architectural and micro-architectural details needed to understand SGX, a detailed and structured presentation of the publicly available information on SGX, a series of intelligent guesses about some important but undocumented aspects of SGX, and an analysis of SGX’s security properties.

Intel SGX Explained.

In order to enable optical systems to operate with a high degree of compactness and reliability it is necessary to combine large number of optical functions in small monolithic structures. A development, somewhat reminiscent of that that took place in Integrated Electronics, is now beginning to take place in optics. The initial challenge in this emerging field, known appropriately as "Integrated Optics", is to demonstrate the possibility of performing basic optical functions such as light generation, coupling, modulation, and guiding in Integrated Optical configurations. The talk will review the main theoretical and experimental developments to date in Integrated Optics. Specific topics to be discussed include: Material considerations, guiding mechanisms, modulation, coupling and mode losses. The fabrication and applications of periodic thin film structures will be discussed.

Integrated optics

Microwave photonics (MWP) is an emerging field in which radio frequency (RF) signals are generated, distributed, processed and analyzed using the strength of photonic techniques. It is a technology that enables various functionalities which are not feasible to achieve only in the microwave domain. A particular aspect that recently gains significant interests is the use of photonic integrated circuit (PIC) technology in the MWP field for enhanced functionalities and robustness as well as the reduction of size, weight, cost and power consumption. This article reviews the recent advances in this emerging field which is dubbed as integrated microwave photonics. Key integrated MWP technologies are reviewed and the prospective of the field is discussed.

Integrated microwave photonics

We present an effective implementation of the Prime Probe side-channel attack against the last-level cache. We measure the capacity of the covert channel the attack creates and demonstrate a cross-core, cross-VM attack on multiple versions of GnuPG. Our technique achieves a high attack resolution without relying on weaknesses in the OS or virtual machine monitor or on sharing memory between attacker and victim.

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Last-Level Cache Side-Channel Attacks are Practical

Cache side channel attacks are serious threats to multi-tenant public cloud platforms. Past work showed how secret information in one virtual machine (VM) can be extracted by another co-resident VM using such attacks. Recent research demonstrated the feasibility of high-bandwidth, low-noise side channel attacks on the last-level cache (LLC), which is shared by all the cores in the processor package, enabling attacks even when VMs are scheduled on different cores. This paper shows how such LLC side channel attacks can be defeated using a performance optimization feature recently introduced in commodity processors. Since most cloud servers use Intel processors, we show how the Intel Cache Allocation Technology (CAT) can be used to provide a system-level protection mechanism to defend from side channel attacks on the shared LLC. CAT is a way-based hardware cache-partitioning mechanism for enforcing quality-of-service with respect to LLC occupancy. However, it cannot be directly used to defeat cache side channel attacks due to the very limited number of partitions it provides. We present CATalyst, a pseudo-locking mechanism which uses CAT to partition the LLC into a hybrid hardware-software managed cache. We implement a proof-of-concept system using Xen and Linux running on a server with Intel processors, and show that LLC side channel attacks can be defeated. Furthermore, CATalyst only causes very small performance overhead when used for security, and has negligible impact on legacy applications.

CATalyst: Defeating last-level cache side channel attacks in cloud computing

Correctly functioning caches have been shown to leak critical secrets like encryption keys, through various types of cache side-channel attacks. This nullifies the security provided by strong encryption and allows confidentiality breaches, impersonation attacks and fake services. Hence, future cache designs must consider security, ideally without degrading performance and power efficiency. We introduce a new classification of cache side channel attacks: contention based attacks and reuse based attacks. Previous secure cache designs target only contention based attacks, and we show that they cannot defend against reuse based attacks. We show the surprising insight that the fundamental demand fetch policy of a cache is a security vulnerability that causes the success of reuse based attacks. We propose a novel random fill cache architecture that replaces demand fetch with random cache fill within a configurable neighborhood window. We show that our random fill cache does not degrade performance, and in fact, improves the performance for some types of applications. We also show that it provides information-theoretic security against reuse based attacks.

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Random Fill Cache Architecture

We propose and experimentally demonstrate a temporal differentiator in optical field based on a silicon microring resonator with a radius of 40 µm. The microring resonator operates near the critical coupling region, and can take the first order derivative of the optical field. It features compact size thus is suitable for integration with silicon-on-insulator (SOI) based optical and electronic devices. The performance of this optical differentiator is tested using signals with typical shapes such as Gaussian, sinusoidal and square-like pulses at data rates of 10 Gb/s and 5 Gb/s.

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Compact optical temporal differentiator based on silicon microring resonator

Newcache is a secure cache that can thwart cache side-channel attacks to prevent the leakage of secret information All caches today are susceptible to cache side-channel attacks, despite software isolation of memory pages in virtual address spaces or virtual machines These cache attacks can leak secret encryption keys or private identity keys, nullifying any protection provided by strong cryptography Newcache uses a novel dynamic, randomized memory-to-cache mapping to thwart contention-based side-channel attacks, rather than the static mapping used by conventional set-associative caches In this article, the authors present an improved design of Newcache, in terms of security, circuit design and simplicity They show Newcache's security against a suite of cache side-channel attacks They evaluate Newcache's system performance for cloud computing, smartphone, and SPEC benchmarks and find that Newcache performs as well as conventional set-associative caches, and sometimes better They also designed a VLSI test chip with a 32-Kbyte Newcache and a 32-Kbyte, eight-way, set-associative cache and verified that the access latency, power, and area of the two caches are comparable These results show that Newcache can be used as L1 data and instruction caches to improve security without impacting performance

Fangfei Liu

Papers

Last-Level Cache Side-Channel Attacks are Practical

CATalyst: Defeating last-level cache side channel attacks in cloud computing

Random Fill Cache Architecture

Compact optical temporal differentiator based on silicon microring resonator

Newcache: Secure Cache Architecture Thwarting Cache Side-Channel Attacks