F
Farhad Merchant
Researcher at RWTH Aachen University
Publications - 42
Citations - 393
Farhad Merchant is an academic researcher from RWTH Aachen University. The author has contributed to research in topics: Computer science & Floating point. The author has an hindex of 10, co-authored 28 publications receiving 271 citations. Previous affiliations of Farhad Merchant include Nanyang Technological University & Indian Institute of Science.
Papers
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Proceedings ArticleDOI
Parameterized Posit Arithmetic Hardware Generator
Rohit B. Chaurasiya,John L. Gustafson,Rahul Shrestha,J. Neudorfer,Sangeeth Nambiar,Kaustav Niyogi,Farhad Merchant,Rainer Leupers +7 more
TL;DR: The architecture of a parameterized PAU generator that can generate PAU adders and PAU multipliers of any bit-width pre-synthesis is presented and it is argued that an n-bit IEEE 754-2008 adder and multiplier can be safely replaced with an m-bit PAU addition and multiplier where m
Journal ArticleDOI
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach
Dominik Sisejkovic,Farhad Merchant,Lennart M. Reimann,Harshit Srivastava,Ahmed Hallawa,Rainer Leupers +5 more
TL;DR: An extensive evaluation of SnapShot for two realistic attack scenarios, comprising both reference combinational and sequential benchmark circuits as well as silicon-proven RISC-V core modules, indicates that the security foundation of common logic locking schemes is built on questionable assumptions.
Journal ArticleDOI
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths
Saptarsi Das,Kavitha T. Madhu,Madhav Krishna,Nalesh Sivanandan,Farhad Merchant,Santhi Natarajan,Ipsita Biswas,Adithya Pulli,S. K. Nandy,Ranjani Narayan +9 more
TL;DR: This paper presents the techniques used to realize arbitrary instruction set extensions (IE) that are identified post-silicon and shows significant improvement in performance for streaming applications over general purpose processor based solutions, by fully pipelining the data-path.
Journal ArticleDOI
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach
Dominik Sisejkovic,Farhad Merchant,Lennart M. Reimann,Harshit Srivastava,Ahmed Hallawa,Rainer Leupers +5 more
TL;DR: In this paper, the security of logic locking has been examined in the context of hardware design and fabrication flow, and it is shown that logic locking is a prominent technique to protect the integrity of hardware designs throughout the integrated circuit design process.
Proceedings ArticleDOI
Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations
Farhad Merchant,Arka Maity,Mahesh Mahadurkar,Kapil Vatwani,Ishan Munje,Madhava Krishna,S. Nalesh,Nandhini Gopalan,Soumyendu Raha,S. K. Nandy,Ranjani Narayan +10 more
TL;DR: This paper carries out extensive micro-architectural exploration for accelerating core kernels like Matrix Multiplication (MM) (BLAS-3) for LU and QR factorizations and achieves up to 8x speed-up for MM in a CGRA environment.