The synthesis of frequency diverse arrays (FDAs) able to achieve time-invariant spatial focusing performance in the short-range is addressed. Two time-modulated optimized frequency offset schemes are presented that allow focusing the energy at a single target location and multiple target locations, respectively. A set of numerical examples is reported and discussed to validate the effectiveness of the proposed solutions also in comparison with the already proposed FDA design approaches.

Synthesis of Time-Modulated Frequency Diverse Arrays for Short-Range Multi-Focusing

This paper presents the design and characterization of a 24-GS/s 3-bit single-core flash analog-to-digital converter (ADC) in 28-nm low-power digital CMOS. It shows the design study of the track-and-hold circuit and subsequent buffer stage and provides equations for bandwidth calculations without extensive circuit simulations. These results are used to target leading-edge speed performance for a single ADC core. The ADC is capable of achieving its full sampling rate without time interleaving, which makes it the fastest single-core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 0.4 W and an effective number of bits of 2.2 at 24 GS/s, the ADC achieves a figure of merit of 3.6 pJ per conversion step while occupying an active area of ${\hbox{0.12 mm}}^{2}$ . Due to its high sampling frequency this ADC can enable ultra-high-speed ADC systems when combined with moderate time interleaving.

Design and Characterization of a 3-bit 24-GS/s Flash ADC in 28-nm Low-Power Digital CMOS

Photonic generation and transmission of linearly chirped microwave waveform with the increased time-bandwidth product (TBWP) is proposed and demonstrated by phase-encoding and splitting parabolic waveform. In the approach, dual-polarization Mach-Zehnder modulator (DPol-MZM) along with polarization controller (PC) is employed to generate two orthogonally polarized wavelengths, and polarization modulator is driven by a parabolic signal. After splitting parabolic waveform and convolving with a binary pseudo random sequence, chirped microwave waveform with high bandwidth and large temporal duration is generated, corresponding to an improved TBWP. Dispersion-induced power fading can be effectively avoided in the approach, and chirped signal with constant initial phase can be achieved by adjusting the PC. The proposed approach is verified by simulations. Linearly chirped microwave waveform with the central frequency of 40 GHz, bandwidth of 12.5 GHz, and TBWP of 20160 is generated. RF spurious suppression ratios of the generated signal are investigated, and pulse compression performances are also analyzed. The system features filter-free, high tunability, compact structure, and large TBWP, which has potential application in the modern radar system.

/pdf/photonic-generation-and-transmission-of-linearly-chirped-lqrylc08gu.pdf

Photonic Generation and Transmission of Linearly Chirped Microwave Waveform With Increased Time-Bandwidth Product

The data rate expected for the forthcoming 5G standard induces stringent constraints for handset transceivers. Wideband carrier aggregation will be handled with flexible and low-power architectures implemented in low-cost technologies. An architecture of a wideband signal generator intended to target sub-6-GHz 5G transmission requirements is presented. The architecture is based on a differential pulse code modulation coding scheme and a custom integrating DAC named the Riemann pump. It performs a 9-dB improvement of the signal-to-noise ratio per doubling of the oversampling ratio while ensuring a flat quantization noise floor over the whole multigigahertz conversion band. Its inherent ability to generate synchronous signals allows us to address carrier aggregation purposes; the generation of 10 synchronized 64-QAM modulated signals between 1.8 and 3.6 GHz is simulated. Postlayout simulations of the Riemann pump implemented in 65-nm CMOS technology fit the exposed theoretical features with a submilliwatt-level power consumption.

A 65-nm CMOS DAC Based on a Differentiating Arbitrary Waveform Generator Architecture for 5G Handset Transmitter

Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs.

Survey of FPGA applications in the period 2000 – 2015 (Technical Report)

Summary form only given, as follows. A pseudo segmented twofold time-interleaved 6-bit DAC occupies 0.28 mm2 chip area in a standard 90 nm CMOS technology. The DAC enables sampling rates up to 28 GS/s with a power consumption of 2.25 W at a −2.5 V power supply. The output bandwidth is at least 14 GHz. The integral nonlinearity (INL) and differential non-linearity (DNL) are 0.8 LSB and 1 LSB respectively. The estimated effective number of bit (ENOB) at 25 GS/s are 5.5-bit at DC and 4.6-bit at the Nyquist frequency.

A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS

A 20 GS/s 3 bit flash ADC with a wide analog bandwidth is realized in a 65 nm CMOS technology. By employing a fourfold parallelization a high sampling rate is achieved, while a large input bandwidth is maintained. The measured effective resolution is between 2 bit and 2.5 bit at a sampling rate of 12.8 GS/s and between 2 bit and 2.3 bit at a sampling rate of 18 GS/s. The power consumption of the ADC core is 2W, the core area is 0.16 mm2.

A 3 bit 20 GS/s flash ADC in 65 nm low power CMOS technology

?This paper presents an arbitrary waveform generator (AWG) based on a 28 GS/s 6 bit digital-to-analog converter (DAC) in a 90 nm CMOS technology [1, 2] and a fieldprogrammable- gate-array (FPGA) board [3]. The sampling rate flexible DAC is bonded on a printed-circuit-board (PCB) offering a real-time interface. Using the FPGA LVDS interfaces arbitrary waveforms up to 1.12 GS/s are generated. This setup is also used to characterize the assembled DAC up to sampling rates of 400 MS/s. The measured spurious-free dynamic range (SFDR) of the DAC is above 40 dB over the whole Nyquist band for a sampling rate of 400 MS/s. FPGA-based real-time synchronization of the high-speed digital inputs is supported by the DAC. Synchronization of the DAC digital inputs is necessary when using the FPGA Rocket-IO (RIO) interfaces. The working principle of the synchronization procedure is proven by measurements allowing future arbitrary waveform generation up to 25 GS/s with the FPGA RIO interfaces and a new DAC board. Keywords - AWG; digital-to-analog-converter; FPGA, Integrated circuit measurements, Measurement techniques

Arbitrary Waveform Generator Based on FPGA and High-Speed DAC with Real-Time Interface

A 25 GS/s 6 bit flash interpolating ADC in 90 nm CMOS technology with an analog input bandwidth of 14 GHz is presented. The ADC is realized in a fourfold parallelized structure to increase the sampling rate and to increase the available settling time in the single ADCs. To improve the linearity several calibration methods are implemented in the circuit. The power consumption of the whole ADC is 2.3 W, resulting in a FOM of 1.9 pJ/step. The converter core area is 0.75 mm2.

A 6 bit 25 GS/s flash interpolating ADC in 90 nm CMOS technology

A Viterbi Equalizer Chip (VEC) which can be applied in 40 Gb/s optical communication systems is presented. The circuit is designed and fabricated in a standard 90 nm CMOS technology with a seven metal layer stack. The internal Viterbi processing is 32 times parallelized using a sliding window decoding architecture at a clock frequency of 1.34 GHz. The VEC processes incoming samples with a resolution of 3 bit. The resolution of the internal branch metrics is 6 bit. The power dissipation at the targeted bitrate of 43 Gb/s is 2.6 W at a supply voltage of 1 V leading to 16.5 Gb/(W·s) which is a 50 times improvement compared to [1]. The chip size is 4.08 mm × 1.40 mm containing almost 500k transistors. The presented circuit is the world first Viterbi equalizer for such a high data rate in any technology. Due to test limitations the measured data rate is 32 Gb/s which is more than three times as fast as previous published [2].

http://ieeexplore.ieee.org/iel7/6679727/6687739/06687782.pdf

Felix Lang

Papers

A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS

A 3 bit 20 GS/s flash ADC in 65 nm low power CMOS technology

Arbitrary Waveform Generator Based on FPGA and High-Speed DAC with Real-Time Interface

A 6 bit 25 GS/s flash interpolating ADC in 90 nm CMOS technology

A Viterbi Equalizer Chip for 40 Gb/s optical communication links