A memory portion and a logic circuit portion of a semiconductor device are formed on a single semiconductor substrate in which a first logic circuit block and a second logic circuit block are formed in different areas and the second logic circuit is located between a pair of memory blocks. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block. A clock signal entered at the center portion of the semiconductor chip is supplied to a plurality of first state clock distributing circuits equidistantly disposed from the center portion and then to a plurality of second stage clock distributing circuits at least equidistantly disposed from each of the first state clock distributing circuits. Next, the clock signal is supplied to a plurality of third state clock distributing circuits equidistantly disposed from each of the second stage clock distributing circuits and then supplied to a plurality of final stage clock distributing circuits equidistantly disposed from each of the third stage clock distributing circuits. From these final stage clock distributing circuits, the clock signal is supplied to an area in whose units an internal gate array and a RAM macro cell or a logic macro cell are made replaceable with each other.

Semiconductor integrated circuit device and method of manufacturing the same

A gate array in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers The function block includes a logic circuit with a first bit storage unit, which is selectively configurable to behave as combinational logic or to store a first bit, and a second bit storage unit, which is also selectively configurable to behave as combinational logic or to store a second bit The matrix of function blocks in accordance with the invention is also useful to properly distribute clocks throughout the gate array

Function block architecture for gate array

An inexpensive, re-configurable storage circuit for programmable logic devices and application specific integrated circuits is disclosed. The storage circuit comprises: at least one output; and at least two inputs; and at least a one input and a two input response sequence, wherein the inputs change the output in a well defined response sequence; and a configuration circuit comprising one or more memory elements, wherein the memory bits are programmed to select one of said response sequences.

Configurable storage device

A delay matching circuit has a first node (48), a second node (50), a first loading circuit (54, 56), a second loading circuit (58, 60), a third loading circuit (64) and a buffer circuit (62). The first loading circuit couples a first logic state to the first node responsive to a first state of a control signal. The second loading circuit couples a second logic state to the first node responsive to a second state of the control signal. The buffer circuit electrically couples the first and second nodes. The first loading circuit, second loading circuit and buffer circuit are characterized by a first, a second and a third predetermined electrical impedance, respectively. The third loading circuit is coupled to the second node and is characterized by a fourth predetermined electrical impedance. The disclosed delay matching circuit propagates a clock signal input with a delay equal to the Clock-to-Q delay associated with a flip-flop constructed with similar circuit elements. The disclosed delay matching circuit is useful in circuits, such as phase locked loops, where the simultaneous propagation of two signals is critical.

Delay matching circuit

An actuator assembly includes a rotatable actuator arm mounted on the base of a disc drive. The actuator arm includes a metallic member seated on a non-metallic body. A proximal end of a load beam is mounted on the actuator arm and a distal end of the load beam supports a head. The actuator assembly also includes a connection between the metallic member and the load beam that secures the load beam to the actuator arm.

Load beam attachment to actuator arm

An apparatus for a transparent master/slave flip-flop logic circuit including a single line connected to the transparency input of the logic macro so that when the line is active input data will pass through the flip-flop, unless the scan signal is also active, in which case the flip-flop will return to a clocked (latching) status.

Transparent flip-flop

A logic cell, for use in a semicustom chip, is comprised of a plurality of transistors that are integrated into a semiconductor substrate and are interconnected within the cell to perform a logic function. This cell has sidewalls which define the space in the chip which contains all the transistors and their interconnections within the cell; at least one of the sidewalls is shaped to include a step which gives the cell a narrow top and a wide bottom; and one or more of the cell's transistors lies below the step in the wide bottom of the cell. Many of these cells are arranged in spaced apart rows on the semicustom chip in which the narrow tops of the cell line up. Conductors which interconnect the cells are disposed in the space between the narrow tops of the cells and over the transistors in the wide bottoms of the cells. Using this architecture, the density with which a logic cell is integrated to a semicustom chip is improved more than 100%.

Semicustom chip whose logic cells have narrow tops and wide bottoms

A synchronizer is comprised of a voltage amplifier having an input terminal for receiving a voltage sample and an output terminal for generating an output voltage that is inversely proportional to the voltage of the input terminal. Also, a first feedback circuit couples the output terminal to a control transistor internal to the amplifier, and a second feedback circuit couples the output terminal to the input terminal. The first feedback circuit together with the control transistor has a fast response time, in comparison to the second feedback circuit; and it operates to quickly increase the output voltage when the voltage sample on the input terminal is below a predetermined level, and vice versa, without altering the voltage sample on the input terminal. And, the second feedback circuit operates to slowly modify the voltage sample on the input terminal in inverse proportion to the output terminal voltage.

Synchronizer having dual feedback loops for avoiding intermediate voltage errors

A synchronizer comprised of a voltage amplifier (10a, 10b, 10d) having an input terminal for receiving a voltage sample (V2) and an output terminal for generating an output voltage (V3) that is inversely proportional to the voltage (V2) of the input terminal. Also, a first feedback circuit (10c) couples the output terminal to a control transistor (10b) internal to the amplifier, and a second feedback circuit (11 and 12) couples the output terminal to the input terminal. The first feedback circuit together with the control transistor has a fast response time, in comparison to the second feedback circuit; and it operates to quickly increase the output voltage when the voltage sample on the input terminal is below a predetermined level, and vice versa, without altering the voltage sample on the input terminal. And, the second feedback circuit operates to slowly modify the voltage sample on the input terminal in inverse proportion to the output terminal voltage.

Synchronizer having dual feedback loops

Une cellule logique utilisee dans une puce a circuit integre prediffuse est constituee d'une pluralite de transistors integres dans un substrat semiconducteur et interconnectes dans la cellule pour assurer une fonction logique. A logic cell used in a chip integrated gate array consists of a plurality of transistors integrated in a semiconductor substrate and interconnected in the cell to provide a logic function. Cette cellule possede des parois laterales (21, 22, 23, 24) qui definissent l'espace dans la puce qui contient tous les transistors et leurs interconnexions dans la cellule. The cell has side walls (21, 22, 23, 24) that define the space in the chip which contains all of the transistors and their interconnections within the cell. Au moins l'une des parois laterales (par exemple 22 et 24) est formee de maniere a presenter un echelon qui confere a la cellule un sommet etroit et une base large. At least one of the side walls (eg 22 and 24) is formed so as to have a level which gives the cell a narrow top and a wide base. Un ou plusieurs transistors de la cellule se trouvent sous l'echelon dans la base large de la cellule. One or more transistors of the cell are under the level in the wide base of the cell. Beaucoup de ces cellules sont agencees en rangees espacees entre elles (R1 et R2) sur la puce a circuit integre prediffuse dans laquelle les sommets etroits de la cellule sont alignes. Many of these cells are arranged in rows spaced apart (R1 and R2) on the integrated circuit gate array chip wherein the narrow peaks of the cell are aligned. Des conducteurs (11) qui connectent les cellules entre elles sont disposes dans l'espace (CH2) entre les sommets etroits des cellules et au-dessus des transistors dans les bases larges des cellules. Conductors (11) which connect the cells together are arranged in the space (CH2) between the narrow peaks of cells and above the transistors in the wide bases of the cells. En utilisant cette architecture, on augmente la densite d'integration de la cellule logique dans une puce a circuit integre prediffuse de plus de 100 %. Using this architecture, we increase the integration density of the logic cell in a gate array integrated circuit chip of more than 100%.

Fernando W. Arraut

Papers

Transparent flip-flop

Semicustom chip whose logic cells have narrow tops and wide bottoms

Synchronizer having dual feedback loops for avoiding intermediate voltage errors

Synchronizer having dual feedback loops

Improved density semicustom integrated circuit chip