High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Three-dimensional ICs provide a promising option to build high-performance compact SoCs by stacking one or more chips vertically. Through silicon vias (TSVs) form an integral component of the 3-D IC technology by enabling vertical interconnections in 3-D ICs. TSV resistance, inductance, and capacitance need to be modeled to determine their impact on the performance of a 3-D circuit. In this paper, the RLC parameters of the TSV are modeled as a function of physical parameters and material characteristics. Models are validated with the numerical simulators like Raphael and Sdevice and with experimental measurements. The TSV RLC model is applied to predict the resistance, inductance, and capacitances of small-geometry TSV architectures. Finally, this paper also proposes a simplified lumped TSV model that can be used to simulate 3-D circuits.

/pdf/electrical-modeling-and-characterization-of-through-silicon-19pwi05t6v.pdf

Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs

This paper describes a digital logic architecture for ‘CMOL’ hybrid circuits which combine a semiconductor–transistor (CMOS) stack and two levels of parallel nanowires, with molecular-scale nanodevices formed between the nanowires at every crosspoint. This cell-based, field-programmable gate array (FPGA)-like architecture is based on a uniform, reconfigurable CMOL fabric, with four-transistor CMOS cells and two-terminal nanodevices (‘latching switches’). The switches play two roles: they provide diode-like I –V curves for logic circuit operation, and allow circuit mapping on CMOL fabric and its reconfiguration around defective nanodevices. Monte Carlo simulations of two simple circuits (a 32-bit integer adder and a 64-bit full crossbar switch) have shown that the reconfiguration allows one to increase the circuit yield above 99% at the fraction of bad nanodevices above 20%. Estimates have shown that at the same time the circuits may have extremely high density (approximately 500 times higher than that of the usual CMOS FPGAs with the same design rules), while operating at higher speed at acceptable power consumption. (Some figures in this article are in colour only in the electronic version)

http://iopscience.iop.org/article/10.1088/0957-4484/16/6/045/pdf

CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices

A method for laying out arrays of components in programmable 2D arrangements with nanometer-scale precision is needed for the manufacture of high density nanoelectronic circuitry. We report programmed self-assembly of gold prototype nanoelectronic components into closely packed rows with precisely defined inter-row spacings by in situ hybridization of DNA-functionalized components to a preassembled 2D DNA scaffolding on a surface. This approach is broadly applicable to the manufacture of nanoscale integrated circuits for logic, memory, sensing, and other applications.

DNA-Templated Self-Assembly of Metallic Nanocomponent Arrays on a Surface

A software energy estimation methodology is presented that avoids explicit characterization of instruction energy consumption and pre-dicts energy consumption to within 3% accuracy for a set of bench-mark programs evaluated on the StrongARM SA-1100 and Hitachi SH-4 microprocessors. The tool, JouleTrack, is available as an online resource and has various estimation levels. It also isolates the switch-ing and leakage components of the energy consumption.

/pdf/jouletrack-a-web-based-tool-for-software-energy-profiling-1r5jydydfp.pdf

JouleTrack: a web based tool for software energy profiling

A digital integrated circuit is described in which the internal registers are organized into a number of serial shift paths to facilitate testing. Each path has a number of modes: USER, HOLD, SHIFT and SELF-TEST modes. These modes are controlled by shifting a control function into a control shift register. When the shifting of the control shift register stops, a command is automatically loaded from the control shift register (or another source) into a command register, which controls the serial shift paths. The provision of a separate command register allows a new control function to be shifted into the control shift register while a preceding command is still active in the command register.

Digital integrated circuits

A digital integrated circuit comprises a number of registers each of which comprises several data bits and at least one control bit cell In a normal operation state, all the registers act as parallel input/output registers In a SHIFT state, the data bits and control bit cells of all the registers are linked together to from a serial shift path between a pair of external terminals allowing test data to be shifted in or out as required In a TEST state, each register is set into one of a number of test modes, controlled by the test bit cells of that register The test modes include a test generate mode in which the register acts as a pseudo-random number generator, and a test analyze mode in which it acts as a digital signature analyzer

Digital integrated circuit with multi-mode register

A digital integrated circuit includes a register (10) having a normal mode of operation in which it acts as a parallel input/ output register. The register also has a second mode of operation in which it acts as a pseudo-random number generator, and a third mode in which it is connected as a circular shift register. This allows the registerto be used forproducing a variety of different test sequences for testing other parts of the circuits e.g. fortesting a programmable logic array included in the circuit.

Testing digital integrated circuits

Data processing apparatus includes a number of units connected by a bus over which each unit can send public write messages to all the other units in parallel. The units are connected in a loop by means of public write acceptance lines. Whenever a unit receives a public write message it sends an acceptance signal to the next unit in the loop. Each unit produces an error signal if it receives a public write message but does ot receive any corresponding acceptance signal, or if it receives an acceptance signal without having received a corresponding public write message. Thus, each unit checks its neighbors in the loop to ensure correct reception of the messages.

Finbar Naven

Papers

Digital integrated circuits

Digital integrated circuit with multi-mode register

Testing digital integrated circuits

Data processing apparatus with message acceptance monitoring

Integrierte digitale schaltungen.