Patent
Digital integrated circuits
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TLDR
Digital Integrated Circuits addresses today's most significant and compelling industry topics, including: the impact of interconnect, design for low power, issues in timing and clocking, design methodologies, and the tremendous effect of design automation on the digital design perspective.Abstract:
A digital integrated circuit is described in which the internal registers are organized into a number of serial shift paths to facilitate testing. Each path has a number of modes: USER, HOLD, SHIFT and SELF-TEST modes. These modes are controlled by shifting a control function into a control shift register. When the shifting of the control shift register stops, a command is automatically loaded from the control shift register (or another source) into a command register, which controls the serial shift paths. The provision of a separate command register allows a new control function to be shifted into the control shift register while a preceding command is still active in the command register.read more
Citations
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Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
TL;DR: Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.
Journal ArticleDOI
Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs
TL;DR: In this paper, the RLC parameters of the TSV are modeled as a function of physical parameters and material characteristics, and a TSV RLC model is applied to predict the resistance, inductance, and capacitances of small-geometry TSV architectures.
Journal ArticleDOI
CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices
TL;DR: In this article, the authors describe a digital logic architecture for CMOL hybrid circuits which combine a semiconductor-transistor (CMOS) stack and two levels of parallel nanowires, with molecular-scale nanodevices formed between the Nanowires at every crosspoint.
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DNA-Templated Self-Assembly of Metallic Nanocomponent Arrays on a Surface
John D. Le,Yariv Pinto,Nadrian C. Seeman,Karin Musier-Forsyth,and T. Andrew Taton,Richard A. Kiehl +5 more
TL;DR: In this article, the authors present a method for self-assembly of gold prototype nanoelectronic components into closely packed rows with precisely defined inter-row spacings by in situ hybridization of DNA-functionalized components to a preassembled 2D DNA scaffolding on a surface.
Proceedings ArticleDOI
JouleTrack: a web based tool for software energy profiling
A. Sinha,Anantha P. Chandrakasan +1 more
TL;DR: A software energy estimation methodology is presented that avoids explicit characterization of instruction energy consumption and pre-dicts energy consumption to within 3% accuracy for a set of bench-mark programs evaluated on the StrongARM SA-1100 and Hitachi SH-4 microprocessors.
References
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Patent
On chip test system for configurable gate arrays
Floyd E. Anderson,Liang-Tsai Lin +1 more
TL;DR: In this article, an on chip test system for arrays is provided that includes self test and maintenance operation while allowing for both synchronous and pipeline modes of normal operation, which is integrated on a chip that includes a plurality of inputs and outputs.
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TL;DR: In this article, a method and apparatus for testing VLSI processors using a bit-sliced bus-oriented data path include data and control monitors and BIT for the on-chip memory.
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Device for loading and reading strings of latches in a data processing system
TL;DR: In this paper, a device for loading data in and reading data out of latch strings located in field replaceable units containing the circuitry of a data processing system realized in accordance with the Level-Scan Sensitive Design (LSSD) technique is described.
Patent
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