We derive the joint equilibrium distribution of queue sizes in a network of queues containing N service centers and R classes of customers. The equilibrium state probabilities have the general form: P(S) - Cd(S) $f_1$($x_1$)$f_2$($x_2$)...$f_N$($x_N$) where S is the state of the system, $x_i$ is the configuration of customers at the ith service center, d(S) is a function of the state of the model, $f_i$ is a function that depends on the type of the ith service center, and C is a normalizing constant. We consider four types of service centers to model central processors, data channels, terminals, and routing delays. The queueing disciplines associated with these service centers include first-come-first-served, processor sharing, no queueing, and last-come-first-served. Each customer belongs to a single class of customers while awaiting or receiving service at a service center but may change classes and service centers according to fixed probabilities at the completion of a service request. For open networks we consider state dependent arrival processes. Closed networks are those with no arrivals. A network may be closed with respect to some classes of customers and open with respect to other classes of customers. At three of the four types of service centers, the service times of customers are governed by probability distributions having rational Laplace transforms, different classes of customers having different distributions. At first-come-first-served type service centers the service time distribution must be identical and exponential for all classes of customers. Many of the network results of Jackson on arrival and service rate dependencies, of Posner and Bernholtz on different classes of customers, and of Chandy on different types of service centers are combined and extended in this paper. The results become special cases of the model presented here. An example shows how different classes of customers can affect models of computer systems. Finally, we show that an equivalent model encompassing all of the results involves only classes of customers with identical exponentially distributed service times. All of the other structure of the first model can be absorbed into the fixed probabilities governing the change of class and change of service center of each class of customers.

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Open, Closed, and Mixed Networks of Queues with Different Classes of Customers

Two simple models of queueing on an N \times N space-division packet switch are examined. The switch operates synchronously with fixed-length packets; during each time slot, packets may arrive on any inputs addressed to any outputs. Because packet arrivals to the switch are unscheduled, more than one packet may arrive for the same output during the same time slot, making queueing unavoidable. Mean queue lengths are always greater for queueing on inputs than for queueing on outputs, and the output queues saturate only as the utilization approaches unity. Input queues, on the other hand, saturate at a utilization that depends on N , but is approximately (2 -\sqrt{2}) = 0.586 when N is large. If output trunk utilization is the primary consideration, it is possible to slightly increase utilization of the output trunks-upto (1 - e^{-1}) = 0.632 as N \rightarrow \infty -by dropping interfering packets at the end of each time slot, rather than storing them in the input queues. This improvement is possible, however, only when the utilization of the input trunks exceeds a second critical threshold-approximately ln (1 +\sqrt{2}) = 0.881 for large N .

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Input Versus Output Queueing on a Space-Division Packet Switch

It is shown that mean queue sizes, mean waiting times, and throughputs in closed multiple-chain queuing networks which have product-form solution can be computed recursively without computing product terms and normalization constants. The resulting computational procedures have improved properties (avoidance of numerical problems and, in some cases, fewer operations) compared to previous algorithms. Furthermore, the new algorithms have a physically meaningful interpretation which provides the basis for heuristic extensions that allow the approximate solution of networks with a very large number of closed chains, and which is shown to be asymptotically valid for large chain populations.

Mean-Value Analysis of Closed Multichain Queuing Networks

1. Introduction 2. Background 3. Performance evaluation process algebra 4. Modelling study: multi-server multi-queue systems 5. Notions of equivalence 6. Isomorphism and weak isomorphism 7. Strong bisimilarity 8. Strong equivalence 9. Conclusions Bibliography Index.

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A Compositional Approach to Performance Modelling

In recent years, considerable effort has focused on evaluating the blocking experienced by "customers" in contending for a commonly shared "resource." The customers and resource in question have typically been messages and storage space in message storage applications or data streams and bandwidth in data multiplexing applications. The model employed in these studies, a multidimensional generalization of the classical Erlang loss model, has been limited to exponentially distributed storage (or data transmission) times, questions concerning efficient computational schemes have largely been ignored, and the class of resource sharing policies considered has been unnecessarily restricted. The contribution of this paper is threefold. We first show that the state distribution (obtained by previous authors) is valid for the large class of residency time distributions which have rational Laplace transforms. Second, we show that, for the important and commonly implemented policy of complete sharing, a simple one-dimensional recursion can be developed which eliminates all difficulty in computing quantities of interest-regardless of both the size and dimensionality of the underlying model. Third, we show that the state distribution holds for completely arbitrary resource sharing policies.

Blocking in a Shared Resource Environment

This paper analyzes the memory interference caused by several processors simultaneously using several memory modules. Exact results are computed for a simple model of such a system. The limiting value is derived for the relative degree of memory interference as the system size increases. The model of the limiting behavior of the system yields approximate results for the simple model and also suggests that the results are valid for a much larger class of models, including those more nearly like real systems than the simple model. The assumptions and results of the simple model are tested against some measurements of program behavior and simulations of systems using memory references from real programs. The model results provide a good indication of the performance that should be expected from real systems of this type.

Interference in multiprocessor computer systems with interleaved memory

This paper describes the fundamentals and some of the details of task communication in DEMOS, the operating system for the CRAY-1 computer being developed at the Los Alamos Scientific Laboratory. The communication mechanism is a message system with several novel features. Messages are sent from one task to another over links. Links are the primary protected objects in the system; they provide both message paths and optional data sharing between tasks. They can be used to represent other objects with capability-like access controls. Links point to the tasks that created them. A task that creates a link determines its contents and possibly restricts its use. A link may be passed from one task to another along with a message sent over some other link subject to the restrictions imposed by the creator of the link being passed. The link based message and data sharing system is an attractive alternative to the semaphore or monitor type of shared variable based operating system on machines with only very simple memory protection mechanisms or on machines connected together in a network.

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Task communication in DEMOS

MIPS is a new single chip VLSI processor architecture It attempts to achieve high performance with the use of a simplified instruction set, similar to those found in microengines The processor is a fast pipelined engine without pipeline interlocks Software solutions to several traditional hardware problems, such as providing pipeline interlocks, are used

MIPS: a VLSI processor architecture

Most new computer architectures are concerned with maximizing performance by providing suitable instruction sets for compiled code and providing support for systems functions. We argue that the most effective design methodology must make simultaneous tradeoffs across all three areas: hardware, software support, and systems support. Recent trends lean towards extensive hardware support for both the compiler and operating systems software. However, consideration of all possible design tradeoffs may often lead to less hardware support. Several examples of this approach are presented, including: omission of condition codes, word-addressed machines, and imposing pipeline interlocks in software. The specifics and performance of these approaches are examined with respect to the MIPS processor.

Forest Baskett

Papers

Open, Closed, and Mixed Networks of Queues with Different Classes of Customers

Interference in multiprocessor computer systems with interleaved memory

Task communication in DEMOS

MIPS: a VLSI processor architecture

Hardware/software tradeoffs for increased performance