Book ChapterDOI
MIPS: a VLSI processor architecture
John L. Hennessy,Norman P. Jouppi,Forest Baskett,John Gill +3 more
- pp 337-346
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TLDR
The MIPS processor is a fast pipelined engine without pipeline interlocks, which attempts to achieve high performance with the use of a simplified instruction set, similar to those found in microengines.Abstract:
MIPS is a new single chip VLSI processor architecture It attempts to achieve high performance with the use of a simplified instruction set, similar to those found in microengines The processor is a fast pipelined engine without pipeline interlocks Software solutions to several traditional hardware problems, such as providing pipeline interlocks, are usedread more
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References
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Proceedings ArticleDOI
RISC I: a reduced instruction set VLSI computer
TL;DR: The architecture of RISC I and its novel hardware support scheme for procedure call/return are presented and it appears possible to build a single chip computer faster than VAX 11/780 and to have a much shorter design time.
Book Chapter
A language for microcode description and simulation in VLSI
TL;DR: A programming language based system for specifying and simulating microcode in a VLSI chip and will drive a PLA layout program to automatically create the PLA.