F
Francis A. Kampf
Researcher at IBM
Publications - 26
Citations - 328
Francis A. Kampf is an academic researcher from IBM. The author has contributed to research in topics: Data compression & Flow control (data). The author has an hindex of 11, co-authored 26 publications receiving 328 citations. Previous affiliations of Francis A. Kampf include GlobalFoundries.
Papers
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Patent
Method and system for improving lossless compression efficiency
TL;DR: In this article, a data segment is compressed utilizing a history buffer to identify repeated character sequences within the data segment, and the history buffer is updated to include a pre-selected data set and reset data from the next data segment.
Patent
Reconfigurable circular bus
TL;DR: In this paper, the authors propose a system that provides communication between a plurality of cores in an integrated circuit, consisting of a circular segmented bus operatively connected to each of the cores for transferring data.
Patent
System of reporting errors by a hardware element of a distributed computer system
Christine M. Desnoyers,Derrick Leroy Garmire,Antoinette Elaine Herrmann,Francis A. Kampf,Robert Frederick Stucke +4 more
TL;DR: In this paper, an error message is generated by a hardware element of a distributed computer system, when an error is detected, and the message is then forwarded from the hardware element to one or more designated processing nodes.
Patent
System and method for correcting timing signals in integrated circuits
Kenneth J. Goodnow,Peter Joel Jenkins,Francis A. Kampf,Jason M. Norman,Sebastian T. Ventrone +4 more
TL;DR: In this article, a system and method for dynamically altering a clock speed of a clock signal used for timing of data signal transmissions and receptions within an integrated circuit (IC) device is presented.
Patent
Simulation testing of digital logic circuit designs
TL;DR: In this article, the authors present a method and system for testing a circuit design, which includes generating a simulation model of the circuit design and running a modified simulation model by inserting random skew between an output of each source latch and an input of the logic function only in asynchronous data paths between the source latches and the destination latches.