Most of the off-the-shelf high-speed Serializer-Deserializer (SerDes) chips do not keep the same latency through the data-path after a reset, a loss of lock or a power cycle. This implementation choice is often made because fixed-latency operations require dedicated circuitry and they are usually not needed for most telecom and data-corn applications. However timing synchronization applications and triggers systems of the high energy physics experiments would benefit from fixed-latency links. In this paper, we present a link architecture based on the highspeed SerDeses embedded in Xilinx Virtex 5 and Spartan 6 Field Programmable Gate Arrays (FPGAs). We discuss the latency performance of our architecture and we show how we made it constant and predictable. We also present test results showing the fixed latency of the link and we finally offer some guidelines to exploit our solution with other SerDes devices.

Fixed-Latency, Multi-Gigabit Serial Links With Xilinx FPGAs

Architecture of EVT4 data acquisition system for electrical capacitance tomography

This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ΔΣ DAC in 65 nm CMOS for the 60 GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1–1 architecture with a 4 bit output resulting in a predominantly digital DAC with only 15 analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the ΔΣ DAC achieves a 53 dB SFDR, -49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed ΔΣ DAC can satisfy the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter.

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An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS

The CBM experiment at the upcoming FAIR accelerator aims to create highest baryon densities in nucleus-nucleus collisions and to explore the properties of super-dense nuclear matter. Event rates of 10 MHz are needed for high-statistics measurements of rare probes, while event selection requires complex global triggers like secondary vertex search. To meet these demands, the CBM experiment uses self-triggered detector front-ends and a data push readout architecture. The First-level Event Selector (FLES) is the central physics selection system in CBM. It receives all hits and performs online event selection on the 1 TByte/s input data stream. The event selection process requires high-throughput event building and full event reconstruction using fast, vectorized track reconstruction algorithms. The current FLES architecture foresees a scalable high-performance computer. To achieve the high throughput and computation efficiency, all available computing devices will have to be used, in particular FPGAs at the first stages of the system and heterogeneous many-core architectures such as CPUs for efficient track reconstruction. A high-throughput network infrastructure and flow control in the system are other key aspects. In this paper, we present the foreseen architecture of the First-level Event Selector.

A First-level Event Selector for the CBM Experiment at FAIR

Radio transmitters are evolving towards digital-intensive solutions to exploit reconfigurability and benefit from CMOS process scaling. Outphasing has been identified as a suitable candidate for digital wideband transmitters. However, with recent digital-intensive outphasing transmitters the achieved performance in terms of adjacent channel leakage ratio (ACLR) has been limited. This paper identifies the sampling images of the modulating phase signal as the main factor limiting the ACLR of digital outphasing transmitters. We present a new digital interpolating phase modulator architecture, capable of providing significantly better sampling image attenuation. When evaluated in outphasing configuration with a 100 MHz OFDM signal at the carrier frequency of 2.46 GHz, and 10-bit phase resolution, the proposed solution achieves an ACLR of $-$ 59 dBc, compared to $-$ 43 dBc achievable with the phase modulator architecture utilized in state-of-the-art digital outphasing transmitters. The proposed digital interpolating phase modulator is also capable of custom carrier generation, a straightforward method for generating an arbitrary carrier frequency up to 1.25 times the phase modulator sampling rate.

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Digital Interpolating Phase Modulator for Wideband Outphasing Transmitters

This paper focuses on the interconnection network used as a part of the Data Acquisition System of the Compressed Baryonic Matter experiment at the Facility for Antiproton and Ion Research in Darmstadt, Germany. This experiment will have special demands on the Data Acquisition System like limited space for hardware, radiation tolerance, flexibility for different types of network traffic and support for synchronization mechanisms. The specialty of the CBM network is that it uses only a single bidirectional fiber link for all network abilities and providing a deterministic latency message for precise time synchronisation. This led to the development of a new network and protocol.

A Unified DAQ Interconnection Network With Precise Time Synchronization

This paper presents an RFDAC based transmitter for wireless mobile and connectivity applications in a 65nm CMOS technology. The transmitter RFDAC has a segmented architecture employing 4 LSB and 16 MSB unit cells for each I and Q path, thus providing a resolution of 8 bit + signum. Switchable LO drivers and unit cells with current shutdown are used to reduce power dissipation when transmitting signals with high PAPR such as IEEE 802.11 (WLAN) or 3GPP Long Term Evolution (LTE). The frontend is capable of transmitting an 64QAM-OFDM WLAN signal at a center frequency of 1 GHz with an output power of −8dBm and an EVM of 4.66 %. Analog power dissipation is 34mW, clock and LO divider use less than 10mW, and the digital block consumes about 87mW. The area of the frontend is about 0.4mm2.

An RFDAC based reconfigurable multistandard transmitter in 65 nm CMOS

This paper focuses on the interconnection network used as a part of the Data Acquisition System of the Compressed Baryonic Matter experiment at the Facility for Antiproton and Ion Research in Darmstadt. This experiment will have special demands on the Data Acquisition System like limited space for hardware, radiation tolerance, flexible enough for all required operation modes of the detectors and support for synchronization mechanisms. The specials of the CBM networks are using only a single bidirectional fiber link for all network abilities and providing a deterministic latency message for precise time synchronisation. This led to the development of a new network and protocol.

A unified interconnection network with precise time synchronization for the CBM DAQ-system

Evolution in high performance computing (HPC) leads to increasing demands on bandwidth, connectivity and flexibility.
Active optical cables (AOC) are of special interest, combining the benefits of electrical connectors and optical
transmission. Optimization and development of AOC solutions requires enhancements concerning different technology
barriers. Area and volume occupied by connectors is of special interest within HPC networks. This led to the
development of a 12x AOC for the mini-HT connector creating the densest AOC available. In order to integrate
electrical optical conversion into a module not higher than 3 mm, a new concept of coupling fibers to VCSELs or
photodiodes had to be developed. This unique concept is based on a direct replication process of an integrated fiber
coupler consisting of a 90° light deflecting and focusing mirror, a fiber guiding structure, and a fiber funnel. The
integrated fiber coupler is directly replicated on top of active components, reducing the distance between active
components and fibers to a minimum, thus providing a highly efficient light coupling. As AOC prototype, multi-chipmodules
(MCM) including the complete electrical to optical conversion for send and receive connected by two 12x fiber
ribbons have been developed. The paper presents the integrated fiber coupling technique and also design and
measurement data of the prototype.

High density active optical cable ― from a new concept to a prototype

This paper focuses on the design and concepts of the hierarchically structured Data Acquisistion (DAQ) network for the Compressed Baryonic Matter (CBM) experiment at the Facility for Antiproton and Ion Research (FAIR) in Darmstadt. Due to the limited physical space and the requirement for a multi TB/s DAQ within the system, this experiment requires compact read-out hardware which provides high bandwidth. Additionally, different detector types must be supported, which requires some flexibility regarding read-out structures and a common synchronization mechanism. Another important goal is to provide hardware that supports an identical interconnection protocol within the complete network to avoid protocol conversions. This led to the design and implementation of modular and unified read-out hardware and firmware.

Frank Lemke

Papers

A Unified DAQ Interconnection Network With Precise Time Synchronization

An RFDAC based reconfigurable multistandard transmitter in 65 nm CMOS

A unified interconnection network with precise time synchronization for the CBM DAQ-system

High density active optical cable ― from a new concept to a prototype

A Hierarchical Synchronized Data Acquisition Network for CBM