Most of the off-the-shelf high-speed Serializer-Deserializer (SerDes) chips do not keep the same latency through the data-path after a reset, a loss of lock or a power cycle. This implementation choice is often made because fixed-latency operations require dedicated circuitry and they are usually not needed for most telecom and data-corn applications. However timing synchronization applications and triggers systems of the high energy physics experiments would benefit from fixed-latency links. In this paper, we present a link architecture based on the highspeed SerDeses embedded in Xilinx Virtex 5 and Spartan 6 Field Programmable Gate Arrays (FPGAs). We discuss the latency performance of our architecture and we show how we made it constant and predictable. We also present test results showing the fixed latency of the link and we finally offer some guidelines to exploit our solution with other SerDes devices.

Fixed-Latency, Multi-Gigabit Serial Links With Xilinx FPGAs

Architecture of EVT4 data acquisition system for electrical capacitance tomography

The CBM experiment at the upcoming FAIR accelerator aims to create highest baryon densities in nucleus-nucleus collisions and to explore the properties of super-dense nuclear matter. Event rates of 10 MHz are needed for high-statistics measurements of rare probes, while event selection requires complex global triggers like secondary vertex search. To meet these demands, the CBM experiment uses self-triggered detector front-ends and a data push readout architecture. The First-level Event Selector (FLES) is the central physics selection system in CBM. It receives all hits and performs online event selection on the 1 TByte/s input data stream. The event selection process requires high-throughput event building and full event reconstruction using fast, vectorized track reconstruction algorithms. The current FLES architecture foresees a scalable high-performance computer. To achieve the high throughput and computation efficiency, all available computing devices will have to be used, in particular FPGAs at the first stages of the system and heterogeneous many-core architectures such as CPUs for efficient track reconstruction. A high-throughput network infrastructure and flow control in the system are other key aspects. In this paper, we present the foreseen architecture of the First-level Event Selector.

A First-level Event Selector for the CBM Experiment at FAIR

Fixed-latency serial links are important components of the distributed measurement and control systems. However, most high-speed Serializer-Deserializer (SerDes) chips do not keep the same link latency after each power-up or reset. In this paper, we propose a fixed-latency serial transceiver based on dynamic clock phase shifting and changeable delay tuning technologies. Our solution can process all possible phase offsets between the transmitted and received clocks, so it relaxes the requirement of fanning in the same reference clock both to the transmitter and to the receiver. It also eliminates the reset-relock process in the roulette approach. We present a specific example of implementation based on the serial transceiver in Xilinx Virtex 5 FPGA. The experiment results indicate that our transceiver can achieve a deterministic latency with sub-nanosecond precision.

Design and FPGA Implementation of High-Speed, Fixed-Latency Serial Transceivers

This paper presents a concept of the Data Processing Boards for the Compressed Baryonic Matter (CBM) experiment.
Described is the evolution of the concepts leading from the functional requirements of the control and readout systems
of the CBM experiment to the design of prototype implementation of the DPB boards. The paper describes requirements
on the board level and on the crate level. Finally it discusses the prototype design prepared for testing and verification of
proposed solutions, and selection of the final implementation.

Data processing boards design for CBM experiment

This paper focuses on the interconnection network used as a part of the Data Acquisition System of the Compressed Baryonic Matter experiment at the Facility for Antiproton and Ion Research in Darmstadt, Germany. This experiment will have special demands on the Data Acquisition System like limited space for hardware, radiation tolerance, flexibility for different types of network traffic and support for synchronization mechanisms. The specialty of the CBM network is that it uses only a single bidirectional fiber link for all network abilities and providing a deterministic latency message for precise time synchronisation. This led to the development of a new network and protocol.

A Unified DAQ Interconnection Network With Precise Time Synchronization

This paper focuses on the interconnection network used as a part of the Data Acquisition System of the Compressed Baryonic Matter experiment at the Facility for Antiproton and Ion Research in Darmstadt. This experiment will have special demands on the Data Acquisition System like limited space for hardware, radiation tolerance, flexible enough for all required operation modes of the detectors and support for synchronization mechanisms. The specials of the CBM networks are using only a single bidirectional fiber link for all network abilities and providing a deterministic latency message for precise time synchronisation. This led to the development of a new network and protocol.

Niels Burkhardt

Papers

A Unified DAQ Interconnection Network With Precise Time Synchronization

A unified interconnection network with precise time synchronization for the CBM DAQ-system