An improved thin-film capacitor and methods for forming the same on a surface of a substrate are disclosed. The capacitor includes a bottom conducting plate formed by depositing conductive material within a trench of an insulating layer and planarizing the conducting and insulating layers. A dielectric film is then deposited on the substrate surface, such that at least a portion of the dielectric material remains over the bottom conducting plate. A second conductive layer is then deposited over the surface of the substrate, patterned and etched such that at least a portion of the second conducting material resides over at least a portion of the dielectric material.

Thin-film capacitors and methods for forming the same

A friction stir welding machine includes a table for supporting parts to be welded and a frame extending over the table. A first drive is supported by a first element of the frame and is operatively connected to a spindle having a tool. The first drive moves the tool in a first direction, and the first drive disengages from the spindle after the tool contacts the material. A second drive is supported by a second element of the frame and is operatively connected to the spindle for moving the tool into the parts at a joint, thereby initiating friction stir welding process. The friction stir welding machine has a pair of rollers mounted in a roller support with an axis of rotation substantially perpendicular to an axis of rotation of the tool. The rollers contact a surface of the material in response to the tool penetrating the material to a desired depth. The roller support is pivotally mounted to the spindle and has a pivot axis substantially perpendicular to both an axis of rotation of the rollers and the axis of rotation of the tool. The work supporting table of the friction stir welding machine has a vacuum hold down system for securing the parts to the table.

Friction stir welding machine and method

A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

Integrated thin film capacitor/inductor/interconnect system and method

An on-chip capacitor includes a first layer first polarity conducting strip and a first layer second polarity conducting strip, wherein the first layer second polarity conducting strip is arranged adjacent to and spaced apart from the first layer first polarity conducting strip, a second layer first polarity conducting strip and a second layer second polarity conducting strip, wherein the second layer second polarity conducting strip is arranged adjacent to and spaced apart from the second layer first polarity conducting strip, wherein the second layer second polarity conducting strip is arranged overlying the first layer second polarity conducting strip, wherein the second layer first polarity conducting strip is arranged overlying the first layer first polarity conducting strip; wherein the first layer first-polarity conducting strip electrically couples with the second layer first polarity conducting strip; and wherein the first-layer second polarity conducting strip electrically couples with the second layer second-polarity conducting strip.

Capacitor structure in a semiconductor device

A method for forming an MIM capacitor, comprising the following steps. A semiconductor structure having an exposed lower metal damascene is provided. A capacitor layer is formed over the semiconductor structure and the exposed lower metal damascene. An organic etch stop layer is formed upon the capacitor layer. An IMD layer is formed upon the organic etch stop layer. The IMD layer is etched with a first etch highly selective to the IMD layer as compared to the organic etch stop layer, to form an IMD trench exposing a portion of the organic etch stop layer. The exposed portion of the organic etch stop layer is etched with a second etch method highly selective to the exposed portion of the organic etch stop layer as compared to the capacitor layer, to expose a portion of the capacitor layer. An upper metal damascene is formed upon the exposed portion of the capacitor layer and within the IMD trench to complete formation of the MIM capacitor.

Fabrication of MIM capacitor in copper damascene process

The present invention provides a method for fabricating a capacitor within a semiconductor device comprising the steps of forming openings in an oxide dielectric to reach a lower conductor layer which will serve as a lower conductor plate of the capacitor; depositing capacitor electrode material, such as tungsten to fill the openings to form a capacitor electrode and planarizing the filled openings using chemical/mechanical polish; depositing a selected oxide capacitor dielectric over the capacitor electrodes and patterning the capacitor dielectric with photoresist to leave dielectric covering the area of the capacitor electrodes; stripping away the photoresist; adding an upper conductor layer on top of the capacitor dielectric to serve as the top plate of the capacitor. The above steps may be repeated to form multiple layers of capacitors within the semiconductor device.

Metal to metal capacitor and method for producing same

Metal-to-metal capacitor having thin insulator

Techniques for estimating a quality of one or more wafers are presented. One or more first wafers comprising one or more first dies are tested. A probability of wafer failure is determined in accordance with one or more first test measurements of the one or more first dies. A pass status and/or a fail status of one or more second wafers is inferred by testing a select one or more second dies of the one or more second wafers and evaluating one or more second test measurements of the select one or more second dies in accordance with the determined probability of wafer failure.

Frederick A. Scholl

Papers

Metal to metal capacitor and method for producing same

Metal-to-metal capacitor having thin insulator

Predicting wafer failure using learned probability