A new silicon controlled rectifier-based power-rail electrostatic discharge (ESD) clamp circuit was proposed with a novel trigger circuit that has very low leakage current in a small layout area for implementation. This circuit was successfully verified in a 40-nm CMOS process by using only low-voltage devices. The novel trigger circuit uses a diode-string based level-sensing ESD detection circuit, but not using MOS capacitor, which has very large leakage current. Moreover, the leakage current on the ESD detection circuit is further reduced, adding a diode in series with the trigger transistor. By combining these two techniques, the total silicon area of the power-rail ESD clamp circuit can be reduced three times, whereas the leakage current is three orders of magnitude smaller than that of the traditional design.

https://ir.nctu.edu.tw:443/bitstream/11536/22701/1/000324928900074.pdf

Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process

A novel PMOS based power supply protection clamp is presented which is designed to operate in a state-of-the art 65 nm, low leakage CMOS process. The design is shown to be amenable to the inherent challenges posed by low cost I/O transistors. Robust ESD and electrical operation is shown as well as immunity to transient latch-up.

A low leakage low cost-PMOS based power supply clamp with active feedback for ESD protection in 65nm CMOS technologies

http://www.ics.ee.nctu.edu.tw/~mdker/Referred%20Journal%20Papers/2014%20MR_Metal-layer%20capacitors%20in%20the%2065%20nm%20CMOS%20process%20and%20the%20application%20for%20low-leakage%20power-rail%20ESD%20clamp%20circuit.pdf

Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit

A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with consideration of the gate leakage issue has been proposed and verified in a 65-nm low-voltage CMOS process. Consisting of the new low-leakage ESD-detection circuit and the ESD clamp device of a substrate-triggered silicon-controlled rectifier, the new proposed power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has a very low leakage current of only 116 nA at room temperature (25°C ) under the power-supply voltage of 1 V. Moreover, the new proposed power-rail ESD clamp circuit can achieve ESD robustness of over 8 kV, 800 V, and over 2 kV in human-body-model, machine-model, and charged-device-model ESD tests, respectively.

https://ir.nctu.edu.tw:443/bitstream/11536/19581/1/000294856900015.pdf

New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process

A power-rail electrostatic discharge (ESD) clamp circuit designed with low-leakage consideration has been proposed and verified in a 65-nm low-voltage CMOS process. By using the metal-oxide-metal (MOM) capacitor in the ESD-detection circuit, the power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has very low stand-by leakage current, as compared to the traditional design. The experimental results in the silicon chip showed that the standby leakage current is only 358 nA at room temperature (25 °C) under the power-supply voltage of 1 V, whereas the traditional design realized with the NMOS capacitor is as high as 828 µA under the same bias condition.

/pdf/design-of-low-leakage-power-rail-esd-clamp-circuit-with-mom-421s2tm9a9.pdf

Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process

A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with the consideration of gate-leakage issue is proposed and verified in a 65-nm low-voltage CMOS process. The new proposed design has a very small leakage current of only 228 nA at 25 °C in the silicon chip. Moreover, it can achieve ESD robustness of over 8kV in human-body-model (HBM) and 750V in machine-model (MM) ESD tests, respectively.

/pdf/on-the-design-of-power-rail-esd-clamp-circuit-with-3e7ylnuqoc.pdf

On the design of power-rail esd clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process

A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25°C, which is much smaller than that (613μA) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.

http://www.ics.ee.nctu.edu.tw/~mdker/International%20Conference%20Papers/2009%20IRPS_Ultra-low-leakage%20power-rail%20ESD%20clamp%20circuit%20in%20nanoscale%20low-voltage%20CMOS%20process.pdf

Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

A method utilizing charged device model (CDM) discharging to emulate real-world charged board model (CBM) discharging was proposed and successfully addressed the weakest spot of whole chip. In order to extract the correlation between CDM pre-fail voltage VCDM and CBM pre-fail voltage VCBM, the capacitance and discharging waveforms of output pin on an IC and printed circuit board (PCB) were measured. The results showed that the CBM evaluation board (EB) was not a must for large-size chip, as LCD driver ICs. CDM discharging can be used to direct investigate the weak point of design/layout for large-size chip. Besides, this paper addresses the guidelines about chip-level ESD cell design and layout optimization against CBM ESD damage.

/pdf/board-level-esd-of-driver-ics-on-lcd-panels-1zxxf4w6gn.pdf

Board Level ESD of Driver ICS on LCD Panels

An electrical overstress failure induced by a latch-up test is studied in high-voltage integrated cricuits. The latchup test resulted in damage to the output NMOSFET due to snapbach and also resulted in a latch-up in the internal circuits. These mechanisms are analyzed and solutions are proposed to avoid the triggering of the output NMOSFET and the resulting latchup issue.

Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits

The ESD robustness of gate-driven ESD clamp circuit in a 16-V CMOS process was investigated by the stresses of transmission line pulse (TLP), human-body-model ESD test, and machine-model (MM) ESD test. After TLP stresses of different voltage steps, the same ESD clamp circuit got different secondary breakdown currents (It2). In order to understand such unusual phenomenon, the failure analysis on the TLP-stressed ESD clamp circuits was performed to find the failure mechanism.

Fu-Yi Tsai

Papers

On the design of power-rail esd clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process

Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

Board Level ESD of Driver ICS on LCD Panels

Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits

Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process