To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to ┌N/M┐ memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the ┌N/M┐ cells. When the bits are read from the cells, the bits are de-interleaved. The interleaving may be deterministic or random, and may be effected by software or by dedicated hardware.

States encoding in multi-bit flash cells for optimizing error rate

The embodiments described herein methods and devices that enhance the endurance of a non-volatile memory (e.g., flash memory). The method includes obtaining, for each of the plurality of die, an endurance metric. The method also includes sorting the plurality of die into a plurality of die groups based on their corresponding endurance metrics, where each die group includes one or more die and each die group is associated with a range of endurance metrics. In response to a write command specifying a set of write data, the method further includes writing the write data to the non-volatile memory by writing in parallel subsets of the write data to the one or more die assigned to a single die group of the plurality of die groups.

Device and method for managing die groups

Provided are memory devices and memory programming methods. A memory device may include a multi-bit cell array including a plurality of multi-bit cells, a programming unit configured to program a first data page in the plurality of multi-bit cells and to program a second data page in the multi-bit cells with the programmed first data page, a first controller configured to divide the multi-bit cells with the programmed first data page into a first group and a second group, and a second controller configured to set a target threshold voltage interval of each of the multi-bit cells included in the first group based on first read voltage levels and the second data page, and to set a target threshold voltage interval of each of the multi-bit cells included in the second group based on second read threshold voltage levels and the second data page.

Memory device and memory programming method

A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods.

Method of error correction in MBC flash memory

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Semiconductor memory device and method of controlling the same

A N-level cell memory controlled by the memory controller of the invention have an internal configuration in which the plurality of data input/output terminals connected to the second data bus are separated into first through Mth data input/output terminal groups, such that there is no redundancy in the n bits of data associated with one N-level cell. Together with this, the memory controller separates the plurality of data bits on the first data bus into first through Mth data groups, the ECC circuits generate error-correction codes for each of these data groups, and the first through Mth data groups and first through Mth error correction codes are input to the first through Mth data input/output terminals of the N-level cell memory, via the second data bus.

Memory controller for multilevel cell memory

PROBLEM TO BE SOLVED: To provide a memory controller to correct errors of read-out data for multi-value cell memory using ECC codes. SOLUTION: N-value (N=2 , n is a larger integer than 2 or it) cell memory MC, which has a plurality of data input/output terminals, has an internal structure, in which n-bit data that belongs to one N-value cell is separated into the first to M data input/output terminal groups without overlapping. The memory controller 2 separates two or more-bit data on a first data but 5 into the first to M data groups, and generates an error correction code in ECC circuits 20 and 22 for each data group. Subsequently, the memory controller 2 inputs the first to M data groups and their error correction codes to the first to M data input/output terminals in the N-value cell memory via a second data bus 6. As a result, n-bit data, which belongs to each N-value cell, is separated into a plurality of ECC zones without overlapping, and an error correction code for data in each ECC zone is generated and stored.

Fujitsu Limited Hideki Kawasaki-shi Kanagawa Arakawa

Papers

Memory controller for multilevel cell memory

Memory controller for multi-value cell memory