An electrical contact (2) and method of making the electrical contact (2), and a connector (11) and method making the connector (11), wherein the electrical contact (2) is an electrically conducting, interlaced mesh (40), with edges of the mesh providing multiple contact points for edgewise electrical connection of the electrical contact (2), wherein the mesh (40) is annealed while restrained in the form of the electrical contact (2) wherein the mesh (40) is free of internal elastic strain, or the mesh (40) is hardened, and wherein the connector (11) retains the electrical contact (2) for edgewise connection.

Electrical contact and connector and method of manufacture

This work investigates electrical pressure contacts based on a micro-spring with orders of magnitude smaller pitch and force than conventional pressure contacts. The springs are beams which curl out of the surface and can be used for wafer-scale testing and packaging. They are fabricated with standard wafer-scale thin film techniques and have been previously demonstrated on active silicon integrated circuits. Single springs and their electrical contacts are characterized with force versus compression and compression versus resistance measurements. Flip-chip packages with hundreds of micro-springs were assembled with 20-mum pad pitch and 40-mum spring pitch. Each spring operates with a force of approximately 0.01 g and contacts a gold pad. These packages are shown to have stable resistance values during both in-situ thermocycle (0degC to 125degC) and humidity testing (60degC at 95%RH). Spring electrical contacts inside the package are shown not to degrade during environmental testing through measurements of four-wire resistance and electrical isolation structures. High-speed glitch measurements are performed to confirm that the pressure contact does not have intermittent opens during thermocycling. These results suggest that a low-force solder-free pressure spring contact is a viable technology for next generation flip-chip packaging

Pressure Contact Micro-Springs in Small Pitch Flip-Chip Packages

This work investigates electrical pressure contacts based on a micro-spring with orders of magnitude smaller pitch and force than conventional pressure contacts. Flip-chip packages were assembled with hundreds of micro-springs at 20 mum pad-pitch, 40 mum spring-pitch, and an operating force of 0.01 gram on gold pads. These packages are shown to have stable resistance values during both in-situ thermocycle (0 degC to 125 degC) and humidity testing (60 degC at 95% RH). High-speed glitch measurements are performed to confirm the pressure contact does not have intermittent opens during thermocycling. These results suggest that a low-force solder-free pressure spring contact is a viable technology for next generation flip-chip packaging

Solder-Free Pressure Contact Micro-Springs in High-Density Flip-Chip Packages

A high-density electrical package utilizing an array of high performance demountable electrical contacts such as UEC, T-Spring, F-Spring and their equivalent contained in a carrier in the form of an interposer between one or more components and a substrate. The carrier is made of a thermally conductive metal or contains thermally conductive metal to provide heat-spreading or dissipation functions in addition to the function of the retention and alignment of the electrical contacts. The above interposer is used for chip attach for a single chip or a stack of chips in the package. The interposer provides electrical connections through individual electrical contact to another chip or to the substrate of the package. It provides also the heat spreading or dissipation function to the chips connected thermally to a particular interposer. The interposer can further be connected thermally to an external heat spreader when necessary.

High Density Electronic Packages

Design guidelimes for a highly reliable three-dimensional die-stacked type module-namely, OUT 3D die-stacked module named "V-STACK", in which four ultra-thin dies (50 pn thick) are vertically stacked and electrically interconnected through copper through-vias in the silicon dies-were devised through the following structural and material analyses. First, stress concentration during temperature cycling (due to the low-rigidity of the ultra-thin die) was investigated by parametric FEM calculations on a VSTACK-type module. The FEM results showed that the stress concentration is mainly caused by the combination of extremely low die rigidity and thermal mismatch between the underfill resin and the gold bumps. It was thus coniiied that controllimg the coefticient of thermal expansion of the underfill resin eliiates the stress concentration in spite of the fact that the dies are ultrathin. Second, optimal combinations of upper and lower bump heights for higher interconnection reliability were determined. Consequently, it was found that several pre-induced defects along the bonding surface greatly reduce interconnection reliability. Finally, the appropriate aspect ratio of the copper through-via structure (i.e., for reducing the tensile stress in the surrounding SOt) was determined from the viewpoint of thermal fatigue in a high-aspect-ratio via structure.

Guidelines for structural and material-system design of a highly reliable 3D die-stacked module with copper through-vias

Electronic packaging continues to produce denser systems. Currently chip packages have more than 1000 I/O, boards have 50-micron lines/spaces, and area array connectors with 1 mm pitch are readily available. To further increase system density, growth into the third dimension (z-axis) is required. However, stacked substrate assemblies have two inherent problems: thermal transfer from the inner layers and reliable, high-density interconnections among all substrates. This paper addresses the result of research on z-axis interconnects suitable for 3-D processor modules. We discuss the advantages and disadvantages for the intended system. One selected interconnection media, which is manufactured by Shin-Etsu, is based on metal wires embedded in a matrix of polymeric material. The wires protrude from the surface of the polymer film. By compressing this material between substrates, contact is made between metallized gold pads on the substrates via the embedded wires. The Shin-Etsu connector allows connections among multiple substrates at 0.5-mm pitch without the need for precision connector alignment because it contains redundant wires at very fine pitch. This paper describes the testing program to determine connector performance and reliability. Daisy chain test vehicles using gold metallization on ceramic substrates were fabricated, assembled and subjected to temperature cycling. Initial test results indicated an incompatibility between the connector material and the substrate, which led to hardware revisions. Daisy chains of 2500 z-axis interconnects have been subjected to over 800 temperature cycles from -45 °C to +85 °C. The resulting system appears to offer a reliable, high-density z-axis interconnection method.

Z-Axis interconnection for 3-D high density packaging

This paper addresses the result of research on Z-axis interconnects suitable for 3-D processor modules. We discuss the advantages and disadvantages for the intended system. One selected interconnection medium, which is manufactured by Shin-Etsu, is based on metal wires embedded in a matrix of polymeric material. The wires protrude from the surface of the polymer film. By compressing this material between substrates, contact is made between metallized gold pads on the substrates via the embedded wires. The Shin-Etsu connector allows connections among multiple substrates at 0.5-mm pitch without the need for precision connector alignment because it contains redundant wires at very fine pitch. The second interconnection method, which is manufactured by FormFactor, uses a wire bonder to create gold wires with spring-like geometries on an array of metallized pads, fabricated on a test socket or interposer. This paper describes the testing program to determine connector performance and reliability.

Alternative Z-axis connector technologies for high-density 3-D packaging

Three-dimensional packaging has been considered by many the best path towards smaller, lighter, faster and less expensive electronics; however, interconnections and efficient thermal transfer have been stumbling blocks towards achieving that goal. Focusing on one of these challenges, this paper examines commercially available z-axis interconnection media, with advantages, disadvantages and selection criteria for the intended system. After an initial down selection based on published data, several connector styles will be tested for life cycle integrity and overall effectiveness for system integration. The primary specifications for the z-axis interconnections are 0.5-mm pitch, area array, high reliability in harsh military environments, and minimal contact force to simplify the external compression structure. This paper also describes the critical nature of the overall structural design and tolerance control, for reliable assemblies and continuous operation; with over two thousand interconnects between each of the five layers in the 3D stack-up.

G. Bates

Papers

Z-Axis interconnection for 3-D high density packaging

Alternative Z-axis connector technologies for high-density 3-D packaging

Z-axis interconnections for high density processors, Part 1