This paper reviews the basic physical mechanisms of the interactions of ionizing radiation with MOS oxides, including charge generation, transport, trapping and detrapping, and interface trap formation. Device and circuit effects are also discussed briefly.

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Total ionizing dose effects in MOS oxides and devices

Electronic devices in space environments can contain numerous types of oxides and insulators. Ionizing radiation can induce significant charge buildup in these oxides and insulators leading to device degradation and failure. Electrons and protons in space can lead to radiation-induced total-dose effects. The two primary types of radiation-induced charge are oxide-trapped charge and interface-trap charge. These charges can cause large radiation-induced threshold voltage shifts and increases in leakage currents. Two alternate dielectrics that have been investigated for replacing silicon dioxide are hafnium oxides and reoxidized nitrided oxides (RNO). For advanced technologies, which may employ alternate dielectrics, radiation-induced voltage shifts in these insulators may be negligible. Radiation-induced charge buildup in parasitic field oxides and in SOI buried oxides can also lead to device degradation and failure. Indeed, for advanced commercial technologies, the total-dose hardness of ICs is normally dominated by radiation-induced charge buildup in either parasitic field oxides and/or SOI buried oxides. Heavy ions in space can also degrade the oxides in electronic devices through several different mechanisms including single-event gate rupture, reduction in device lifetime, and large voltage shifts in power MOSFETs.

Radiation Effects in MOS Oxides

We report electron spin resonance (ESR) measurements of E′‐center (a ‘‘trivalent silicon’’ center in SiO2) density as well as capacitance versus voltage (C‐V) measurements on γ‐irradiated metal/oxide/silicon (MOS) structures. We also report a considerable refinement of earlier ESR measurements of the dependence of radiation‐induced Pb ‐center (a ‘‘trivalent silicon’’ center at the Si/SiO2 interface) occupation as a function of the Fermi level at the Si/SiO2 interface. These measurements indicate that the Pb centers are neutral when the Fermi level is at mid‐gap. Since the Pb centers are largely responsible for the radiation‐induced interface states, one may take ΔVmg Cox/e (where ΔVmg is the ‘‘mid‐gap’’ C‐V shift, Cox is the oxide capacitance, and e is the electronic charge) as the density of holes trapped in the oxide. We find that radiation‐induced E′ density equals ΔVmg Cox/e in oxides grown in both stream and dry oxygen. Etch‐back experiments demonstrate that the E′ centers are concentrated very near the Si/SiO2 interface (as are the trapped holes). Furthermore, we have subjected irradiated oxide structures to a sequence of isochronal anneals and find that the E′ density and ΔVmg annealing characteristics are virtually identical. We conclude that the E′ centers are largely responsible for the deep hole traps in thermal SiO2 on silicon. This observation coupled with observations regarding the Pb center indicates that two intrinsic centers, both involving silicon atoms lacking one bond to an oxygen atom, are largely responsible for the two electrically significant aspects of radiation damage in MOS devices: charge buildup in the oxide and interface‐state creation at the Si/SiO2 interface.

Hole traps and trivalent silicon centers in metal/oxide/silicon devices

A characteristic interface trap was observed in a hole trapping experiment when electrons were captured by trapped holes injected by an avalanche in the silicon. The observations could be explained by the generation of new electronic states through relaxation of strained bonds which were proposed to be the origin of hole traps. The result is either a weak bond in the network or two dangling bonds with no net charge. The weak bond or dangling bonds give rise to neutral traps in the bulk and interface traps at the interface of the oxide. The presence of interface traps for such defects at the interface is predicted by theoretical calculations.

Interface trap generation in silicon dioxide when electrons are captured by trapped holes

The breakdown of thin oxides (7.9-32 nm) subjected to high-field current injection is investigated in this study. The physical mechanism of breakdown is found to be localized field enhancement at the cathode interface due to hole trapping. The source of this hole trapping is believed to be impact ionization in the SiO 2 . A quantitative model for oxide breakdown based on impact ionization and hole trapping at the cathode is presented and shown to agree well with the experimental J - t and time-to-breakdown, (t BD ) results. We observe that log t BD varies linearly with 1/ E rather than with E as commonly assumed. The field acceleration factor, i.e., the slope of the log t BD versus 1/ E plot, is approximately 140 decades per centimeter per megavolt for the 7.9 nm oxide, with approximately 25 percent of this coming from the field dependence of the impact ionization coefficient and the remainder from the Fowler-Nordheim current dependence on 1/ E . Based on this model, oxide wearout performance might be improved by process changes that reduce interface hole trapping, such as radiation-hard processing, in addition to the reduction of particulate contamination and crystal defects.

Electrical breakdown in thin gate and tunneling oxides

The effects of processing steps on the radiation hardness of MOS devices have been systematically investigated. Quantitative relationships between the radiation-induced voltage shifts and processing parameters have been determined, where possible. Using the results of process optimization, a controlled baseline fabrication process for aluminum-gate CMOS has been defined. CMOS inverters which can survive radiation exposures well in excess of 108 rads (Si) have been fabricated. Restrictions that the observed physical dependences place upon possible models for the traps responsible for radiation-induced charging in SiO2 are discussed.

Process Optimization of Radiation-Hardened CMOS Integrated Circuits

Exposure of MOS devices to different dose-rate ionizing radiation environments indicates an apparent dependence of radiation charging upon the dose rate. It is shown in this paper that over a wide range of dose rates there is no true dose rate dependence and that the differences in radiation charging can be attributed to annealing effects. It is shown that convolution integrals and linear system theory accurately predict charging behavior and that the impulse response of the system can accurately be predicted for very long times since the annealing phenomenon is temperature activated.

CMOS Hardness Prediction for Low-Dose-Rate Environments

A model is presented which relates MOS processing steps and design parameters to the ionizing radiation sensitivity of hardened MOS devices. The model is based on combining the viscous properties of SiO/sub 2/ at typical processing temperatures with stresses arising in the SiO/sub 2/ on Si system during oxidation and subsequent high-temperature cycles. The model explains the recently observed dependence of radiation-induced flatband voltage shifts upon SiO/sub 2/ thickness cubed. Quantitative comparison with experiment is obtained for the relations of flatband voltage shift on post-oxidation annealing temperature and on oxide growth temperature. Several processing changes to further harden both dry and wet oxides are suggested by the model.

Viscous Shear Flow Model for MOS Device Radiation Sensitivity

A major disadvantage of bulk CMOS integrated circuits is that they can exhibit SCR behavior when exposed either to modest levels of ionizing radiation (?? ? 108 rads (Si)/sec) or to an overvoltage (which is typically less than the substrate to p-well avalanche voltage). This paper discusses the successful application of gold-doping to CMOS integrated circuits to control substrate minority carrier lifetime, thus preventing latch-up. Data is presented showing the effects of the gold-doping upon junction integrity, oxide charge, surface state density, and radiation hardness. Junction arrays and split lots of a CMOS LSI circuit were fabricated to demonstrate that the gold-doped process does not reduce device yield. Data after bias-temperature stress-aging indicates that there is no statistically significant difference in the reliability between gold-doped and undoped CMOS circuits.

Prevention of CMOS Latch-Up by Gold Doping

Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre-and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented.

G. F. Derbenwick

Papers

Process Optimization of Radiation-Hardened CMOS Integrated Circuits

CMOS Hardness Prediction for Low-Dose-Rate Environments

Viscous Shear Flow Model for MOS Device Radiation Sensitivity

Prevention of CMOS Latch-Up by Gold Doping

Design Optimization of Radiation-Hardened CMOS Integrated Circuits