A method and structure for providing ESD protection for Silicon-On-Insulator (SOI) integrated circuits. The ESD protection circuit includes an electrically conductive pad and first conductor segment fabricated over an insulating layer. The first conductor segment connects the pad directly to a first node, without an intervening input resistor. A first diode is fabricated over the insulating layer and connected between the first node and a first voltage supply rail. Similarly, a second diode is fabricated over the insulating layer and connected between the first node and a second voltage supply rail. Ballast resistors can be included in series with each of the diodes. A cross power supply clamp, also fabricated over the insulating layer, is connected between the first and second voltage supply rails. The first node of the ESD protection circuit is coupled to the SOI integrated circuit to be protected. The ESD protection circuit can be fabricated on a minimum number of silicon islands to improve local thermal spreading. Improved ESD protection is provided to input, output, and I/O pins of an SOI integrated circuit, while promoting high speed signal transfer between these pins and the integrated circuit.

Method and structure for providing ESD protection for silicon on insulator integrated circuits

A diffused resistor and a method for making the diffused resistor are disclosed The diffused resistor is formed in a substantially pure portion of the thin semiconductor layer that is formed on an insulating substrate The thin semiconductor layer has low a number of defects and mid-band gap states This portion may be located in an electrically isolated region of the thin semiconductor layer A resistive region is used to provide the resistance of the diff-used resistor Contact regions are provided continguous with the the resistive region The diff-used resistor can be formed by themselves or in conjunction with other circuit elements, such as a MOSFET, for example Accordingly, also disclosed is a method for making the diffused resitor in conjunction with a MOSFET The diffused resistor and the MOSFET are formed in electrically isolated semiconductor islands The electrically isolated semiconductor islands are formed from the high quality thin semiconductor layer Both non-silicide and silicide processes are disclosed Also disclosed is a differential amplifier circuit that uses the disclosed diffused resistor embodiments

Method of making a low parasitic resistor on ultrathin silicon on insulator

An improved process and structure for channel stop in silicon on insulator using LOCOS isolation are disclosed. Advantages include decreased ion dose requirements; reduced processing time; smaller ΔW characteristics, thus, small transistor size and more precise process control over the edge of a MOSFET. the process also makes possible a wide range of transistor design capabilities and improved transistor operating parameters.

Self-aligned edge control in silicon on insulator

Electrostatic discharges (ESDs) are everywhere-in our homes and businesses. Even the manufacturers of the electronics experience ESD failures in their factories. Electronic devices are sensitive to ESD. ESD results in failure of our computers, calculators, and car phones. There are ways to protect these sensitive components. This paper looks at ESD protection from a two-pronged approach: reducing the likelihood of having an ESD event and improving the robustness of the devices themselves. The first approach focuses on reducing the amount of charge that is developed and controlling the redistribution of any charges that are developed The second approach reviews ways to improve the circuit robustness by improving individual circuit elements and by adding additional elements for charge flow control and voltage clamping.

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Electrostatic discharge in semiconductor devices: protection techniques

ESD robustness of 4 kV HBM is achieved in CMOS-on-SOI ESD protection networks in an advanced sub-0.25 /spl mu/m CMOS-on-SOI technology. Design layout, body contact, floating gate effects and novel ESD protection implementations are discussed.

CMOS-on-SOI ESD protection networks

A protective network for silicon-gate C-MOS/SOS arrays has been designed that is capable of protecting input circuits from static discharges in excess of 2200 V. This paper describes the results of a program undertaken at RCA to develop a protection network for C-MOS arrays on sapphire substrates capable of withstanding 1500-v static discharges. A test chip with eight input protection configurations was designed, processed, and tested. The results were incorporated into a network design that exceeds the requirements without degrading circuit speed.

G.K. Caswell

Papers

An improved input protection circuit for C-MOS/SOS arrays