A serial multiplier suitable for VLSI implementation is discussed. The multiplier accepts binary operands supplied in a serial fashion, least significant bits first. The multiplier uses a canonical cell which allows calculation of a 2k length product with only k identical cells. These cells utilize the carry-save addition technique to provide a delay which exhibits only a first-order dependence on the number of bits in the product. The internal logic for generating the inputs to the carry-save adders is given. This cell directly accepts the bit-serial inputs and generates a bit-serial output. Longer binary operands can be multiplied by simply cascading identical cells without change to existing cells. A given multiplier can process shorter operands in correspondingly shorter times. Applicability of this technique to VLSI implementation of the basic multiply/add operation useful in signal processing algorithms is described.

A Canonical Bit-Sequential Multiplier

A single-chip per channel codec with filters, fabricated using a single poly-Si NMOS technology, is discussed In the encoder, the analog signal is converted to a 2048 M samples/s digital signal by a /spl Delta/-/spl Sigma/ modulator Filtering necessary for the sampling rate 8 k sample/s and compression by the /spl mu/255 law are performed digitally In the decoder, the 8 k samples/s PCM is successively resampled and converted into the 2048 M samples/s /spl Delta/-/spl Sigma/ signal, which is then decoded by a /spl Delta/-/spl Sigma/ demodulator All the high-frequency images, which appear around multiples of 8 kHz, are removed by digital filters The chip has continuous-signal antialiasing and smoothing filters for the 2048 Samples/s sampling rate It also has reference voltage generators for /spl Delta/-/spl Sigma/ modulation/demodulation Some of the observed characteristics are given The NMOS /spl Delta/-/spl Sigma/ modulator requires only two on-chip matched capacitors as precision components, and does not require a linear amplifier A deliberate quantization step imbalance is introduced to allow a low sampling rate The main band limiting for the 8 k samples/s is done by the recursive filter This is realized with the serial-parallel pipeline multiplier (SPPM) in four-phase logic The whole system is integrated on a 296 mil/spl times/342 mil chip

Single-chip per channel codec with filters utilizing /spl Delta/-/spl Sigma/ modulation

Using a standard 6 /spl mu/m NMOS silicon-gate process, circuit techniques are described for the full integration of high-speed ROM-accumulator and multiplier type digital filters. The ROM-accumulator structure is integrated using a new two-clock four-phase technique which can be used both for ROM and accumulator. An operating speed of 20 Mbits/s is measured. The circuit shows that an eighth-order filter on a 20 mm/SUP 2/ chip, dissipating only 400 mW at 10 Mbits/s is feasible. Using a 4-clock 4-phase technique a 4-bit serial-parallel multiplier is presented featuring 20 Mbits/s operation into a 15 pF load. Power dissipation is 7 mW/cell. Cell area is 0.2 mm/SUP 2/.

High-speed NMOS circuits for ROM-accumulator and multiplier type digital filters

Bit-sequential algorithms for arithmetic processing are good candidates for VLSI signal processing circuits because of their canonical structure and minimal interconnection requirements. Several recent papers have dealt with algorithms that accept unsigned binary inputs, one bit at a time, least significant bit first, and produce an unsigned binary product in a bit-serial fashion.

A Signed Bit-Sequential Multiplier

The authors describe high-performance CMOS LSIs for digital signal-processing (DSP) technology, such as digital filter, fast Fourier transform (FFT), discrete Fourier transform (DFT), and digital phase-locked loop (DPLL), for communication use. Device design for high-speed and low-power CMOS is described and its feasibility is shown as characteristics of propagation delay time and power delay product.

LSIs for digital signal processing

Describes the design and implementation of a 44 Mbit/s serial pipeline multiplier that exploits an efficient algorithm with a novel circuit architecture. The multiplier, intended for use with signed-magnitude coefficients and two's complement data of arbitrary length, produces products automatically rounded and truncated to the same length as incoming data. The circuit's design focuses on the bit-cell, a unit of circuitry associated with one bit of the coefficient word, from which multipliers of arbitrary complexity may be constructed. A practical realization of this multiplier contains four bit-cells, each of which dissipates 20 mW, as well as all associated data, coefficient, and control registers necessary for its operation. The total power dissipation for the chip is 140 mW. The physical implementation of the multiplier employs buried-collector bipolar devices and two-level aluminum metallization to obtain a compact chip 120 mil/SUP 2/. Descriptions of the circuit's arithmetic architecture, design, performance, and use are given in detail.

G.L. Baldwin

Papers

A modular, high-speed serial pipeline multiplier for digital signal processing