We investigate for the first time the reliability of the direct copper bonding process. Electromigration (EM) and Stress Induced Voiding (SIV) tests are performed on intensive 30000 daisy chains and emphasize the good behaviour facing the risk of reliability issues in Cu/Cu bonded interconnects achieved by a direct low temperature (200°C) bonding. Furthermore, a comparison between stand alone and bonded device shows that the metallic bonding interfaces do not impact on the failure mechanism during EM tests.

Investigation of stress induced voiding and electromigration phenomena on direct copper bonding interconnects for 3D integration

Micro-displays based on micro-LEDs are becoming more and more attractive in AR/MR (Augmented/Mixed Reality) applications. A display size of 0.5 to 0.7-inch is preferred, with 5,000 PPI (Pixel Per Inch) or higher. Due to this pixel density and size, a CMOS (Complementary Metal-Oxide-Silicon) backplane is an ideal solution to drive these pixelized micro-LEDs. As the required pixel size gets smaller, the design of the appropriate pixel circuit becomes more challenging. The simplest 2T1C (2 transistors & 1 capacitor) pixel circuit has potential problems, due to the leakage current of the switch transistor and the voltage drop on the matrix array layout. In this paper, a pixel circuit is proposed as a solution to overcome these two issues. Our simulation results show that the variation of the driving current to the LED is improved by 95 %, and the IR drop error rate is around 2.2 % compared to the 2T1C circuit. The test results also show that the error rate of IPIXEL for the whole region of display is under 2.5 %. This work is verified using a test chip implementation with 180 nm CMOS process technology.

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CMOS Backplane Pixel Circuit With Leakage and Voltage Drop Compensation for an Micro-LED Display Achieving 5000 PPI or Higher

The recent developments of wafer-to-wafer bonding technology based on direct assembly of inorganic dielectric materials is offering a path for the continuous need for higher integration density and lower interconnect pitches. However, numerous applications could benefit of a higher degree of design flexibility offered by a die-to-wafer approach. The achievement of high yielding die-to-wafer bonding with micron range die overlay is an essential element to unlock the potential of heterogeneous integration.

Enabling Ultra-Thin Die to Wafer Hybrid Bonding for Future Heterogeneous Integrated Systems

Plasma- and water-assisted oxide-oxide thermocompression direct bonding for a self-assembly based multichip-to-wafer (MCtW) 3D integration approach was demonstrated. The bonding yields and bonding strengths of the self-assembled chips obtained by the MCtW direct bonding technology were evaluated. In this study, chemical mechanical polish (CMP)-treated oxide formed by plasma-enhanced chemical vapor deposition (PE-CVD) as a MCtW bonding interface was mainly employed, and in addition, wafer-to-wafer thermocompression direct bonding was also used for comparison. N2 or Ar plasmas were utilized for the surface activation. After plasma activation and the subsequent supplying of water as a self-assembly mediate, the chips with the PE-CVD oxide layer were driven by the liquid surface tension and precisely aligned on the host wafers, and subsequently, they were tightly bonded to the wafers through the MCtW oxide-oxide direct bonding technology. Finally, a mechanism of oxide-oxide direct bonding to support the previous models was discussed using an atmospheric pressure ionization mass spectrometer (APIMS).

Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration.

vii Titel: Optical sensor array based Nanospectrometer: Fabrication of high resolution 3D NanoImprint master templates and bonding of Fabry-Pérot filter array onto photodetector array Author: Muhammad Ikram Hafiz Department: Technological Electronics, Dept. of Electrical Engineering & Computer Science, University of Kassel, Germany Reviewer: Prof. Dr. H. Hillmer Prof. Dr. P. Lehmann

Optical Sensor Array based Nanospectrometer: Fabrication of high resolution 3D NanoImprint master templates and bonding of Fabry-Pérot filter array onto photodetector array

We demonstrate chip to wafer assembly based on aligned Cu-Cu direct bonding. A collective die surface preparation for direct bonding has implemented to develop dies direct bonding, defect free. An accurate pick and place equipment was adapted to ensure a particle free environment. After a damascene-like surface preparation, chips were bonded with less than 1μm misalignment. 400°C bonded daisy chains on die to wafer structure are perfectly ohmic. Concurrently, to overcome speed limitation of pick and place technique, a self-assembly technique chip is developed. This technique is based on capillary effect for self alignment and direct bonding for assembly. A less than 1 μm alignment accuracy and a 90 per cent self assembly process yield are obtained.

G. Lecarpentier

Papers

Chip to wafer direct bonding technologies for high density 3D integration