Simulation of quantum systems is expected to be one of the most important applications of quantum computing, with much of the theoretical work so far having focused on fermionic and spin-
 $$\frac{1}{2}$$
 systems. Here, we instead consider encodings of d-level (i.e., qudit) quantum operators into multi-qubit operators, studying resource requirements for approximating operator exponentials by Trotterization. We primarily focus on spin-s and truncated bosonic operators in second quantization, observing desirable properties for approaches based on the Gray code, which to our knowledge has not been used in this context previously. After outlining a methodology for implementing an arbitrary encoding, we investigate the interplay between Hamming distances, sparsity patterns, bosonic truncation, and other properties of local operators. Finally, we obtain resource counts for five common Hamiltonian classes used in physics and chemistry, while modeling the possibility of converting between encodings within a Trotter step. The most efficient encoding choice is heavily dependent on the application and highly sensitive to d, although clear trends are present. These operation count reductions are relevant for running algorithms on near-term quantum hardware because the savings effectively decrease the required circuit depth. Results and procedures outlined in this work may be useful for simulating a broad class of Hamiltonians on qubit-based digital quantum computers.

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Resource-efficient digital quantum simulation of d-level systems for photonic, vibrational, and spin-s Hamiltonians

Advances in flexible and stretchable electronics, functional nanomaterials, and micro/nano manufacturing have been made in recent years. These advances have accelerated the development of wearable sensors. Wearable sensors, with excellent flexibility, stretchability, durability, and sensitivity, have attractive application prospects in the next generation of personal devices for chronic disease care. Flexible and stretchable wearable sensors play an important role in endowing chronic disease care systems with the capability of long-term and real-time tracking of biomedical signals. These signals are closely associated with human body chronic conditions, such as heart rate, wrist/neck pulse, blood pressure, body temperature, and biofluids information. Monitoring these signals with wearable sensors provides a convenient and non-invasive way for chronic disease diagnoses and health monitoring. In this review, the applications of wearable sensors in chronic disease care are introduced. In addition, this review exploits a comprehensive investigation of requirements for flexibility and stretchability, and methods of nano-based enhancement. Furthermore, recent progress in wearable sensors—including pressure, strain, electrophysiological, electrochemical, temperature, and multifunctional sensors—is presented. Finally, opening research challenges and future directions of flexible and stretchable sensors are discussed.

Non-Invasive Flexible and Stretchable Wearable Sensors With Nano-Based Enhancement for Chronic Disease Care

Improved instantneous frequency estimation using an adaptive short-time fourier transform

Gate diffusion input (GDI) method using a simple cell makes it possible to design low-power logic gates with reduced chip area and less complexity. In this work, a novel design of single-bit optimized reversible logic-based magnitude arithmetic unit (RMAU) circuit, using appropriate standard reversible gates with carbon nanotube (CNT) field-effect transistors (CNTFETs), based on modified-GDI (m-GDI) method for nanoscales is presented. In order to optimize the performance of the proposed circuit, and to achieve minimum power consumption and propagation delay, transistor sizes are adjusted using the non-dominated sorting genetic algorithm II (NSGA-II) in MATLAB tool. The simulation results show improvement in evaluating the figure of merits in worst-case delay and power consumption of the proposed optimized arithmetic unit, in comparison with a non-optimized RMAU circuit using a similar design method but counterpart structures. The effects of different process parameters (such as the diameter of CNTs) and voltage and temperature (PVT) variations are extensively evaluated by the Monte Carlo procedure in standard 32 nm technology utilizing the Synopsys HSPICE simulator. According to the outcomes obtained, the proposed optimized RMAU circuit is robust against PVT variations and noise-tolerable criterions, compared to those competitors with similar design in non-optimized conditions. The proposed optimized and non-optimized circuits were used in image processing as real environment assessments, and results depicted their excellent ability in being implemented in various large reversible-based applications, such as future generations of FPGA chips and CNTFET-based computers.

Optimized Gate Diffusion Input Method-Based Reversible Magnitude Arithmetic Unit Using Non-dominated Sorting Genetic Algorithm II

In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.

Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2’s Complement Code Converter

Nowadays reversible circuit designing is the emerging area of research. This design strategy aims towards the formation of digital circuits with ideally zero power dissipation. In this paper we have proposed a new reversible logic module to design a 4-bit binary 2"s complement circuit. This complement circuit using reversible logic can be used to design other low loss Arithmetic circuit. Proposed circuits have been simulated using ModelSim and implemented using Xilinx Spartan2 FPGA platform. General Terms 2"s complement calculator. Keywordslogic circuit, Reversible gates. gates. These designs are optimized on the basis of the total number of reversible gates used in the design, total number of garbage outputs and macro statistics etc. Later we have proposed a highly optimized circuit for 2"complement calculator using a single SSMT gate. SSMT gate is introduced in this paper. This gate can be used for the designing of various arithmetic and logical applications, but in this paper its application is limited to 2"s complement calculator only. The paper is organized in nine sections. First section gives the introduction of the proposed 2"s complement calculator circuit using the reversible logic concept. Section two gives the brief introduction of the fundamental concepts of reversible logic. Next section introduces the proposed reversible gate i.e. SSMT gate. After that in section four conventional 2"s complement calculator for 4-bit binary numbers is discussed. In section five designing of 4-bit 2"s complement calculator circuit using reversible gates have been performed. Result and analysis of the proposed designs have been given in section six. Sections seven, eight and nine give the conclusion, acknowledgement and references of the paper respectively. 2. FUNDAMENTALS OF REVERSIBLE

https://research.ijcaonline.org/ICCCMIT/number2/icccmit1012.pdf

Design of a 4-bit 2's Complement Reversible Circuit for Arithmetic Logic Unit Applications

This paper proposes a new architecture of 2-D block FIR filter using distributed arithmetic (DA) algorithm, which is known for the efficient design of multiply and accumulate block. Hardware-based architecture is proposed for DA lookup table (DA-LUT) that makes the architecture of 2-D FIR filter reconfigurable. Further, due to block processing, sharing takes place among DA-LUTs at various stages. Thus, a common DA-LUT may be designed for block inputs which reduce the hardware complexity for DA-LUT. Furthermore, memory overlapping is used to reduce the systolic architectures in proposed design over existing designs. For higher-order 2-D FIR filter, the complexity of DA-LUT is reduced by dividing the internal block into parallel and small blocks. With the help of ASIC synthesis results, a comparative analysis of proposed design with the earlier reported designs is presented, and it is shown that the proposed design leads to significant improvements in various performance parameters.

High-Throughput, Area-Efficient Architecture of 2-D Block FIR Filter Using Distributed Arithmetic Algorithm

As we know that developments in technology are introducing various methods for Tele-cardiology. Tele-cardiology includes many of the applications and this is one of the fields in telemedicine which have seen excellent growth. In the procedures of Tele-cardiology we record a extremely large amount of ECG real time data. Therefore we require an efficient and lossless technique that is able to perform compression of recorded ECG signals. In this paper we have studied and analyzed various lossless data compression techniques used in the compression of ECG signals. In the course of studying various techniques we have presented the analysis of some most widely used time domain techniques those are AZTEC (Amplitude zone time epoch coding) technique and Turning point technique (TP) and in transformation based compression techniques we have presented the study of Discrete Cosine Transform technique (DCT) performed with Huffman coding technique and Empirical Mode Decomposition (EMD) technique. The overall performance of all these techniques are studied and analyzed on the basis of two main parameters those are the compression ratio (CR) and Percent Root means square Difference (PRD). We have used the data base of physionet.org website for the calculation of CR and PRD. We have calculated and compared the CR and PRD values using all above discussed techniques for 28 sets of the recorded data.

Study of various data compression techniques used in lossless compression of ECG signals

The approach of designing digital circuits using reversible logic concept is gaining more and more attention of the researchers due to its characteristics of generating low-loss or ideally loss-less systems. This area of circuit designing is gaining wide application in the field of low power computing, optical computing, quantum computing, low power VLSI designs etc. Researchers are working in the field of designing various sequential as well as combinational subsystems of the computer using reversible logic concept. Here we have presented a design approach for array multiplier using Reversible logic approach. This circuit can be further modified and explored to further design various low-loss computing devices.

Design of array multiplier circuit using reversible logic approach with optimized performance parameters

In this research article we have explained the design and fabrication process of ECG patch electrodes that are highly stretchable, flexible and almost similar to skin these electrodes are going to be used in the long term and unconscious sensing of electrical activity of heart. The overall design and fabrication process is highly motivated by the developments of the nanotechnology. As the result of these developments in nanotechnology we are able to reduce the size, cost, and power requirements of the electrodes used in the sensing of various bio signal, in our design we have used the Carbon NanoTube (CNT) / PolyDiMethylSiloxane (PDMS) composite material for the fabrication of patch electrodes. These electrodes provides better performance over conventional electrodes and one more important thing is that these microelectrodes are waterproof and hence patient can also be monitored at the time of showering.

G. R. Mishra

Papers

Design of a 4-bit 2's Complement Reversible Circuit for Arithmetic Logic Unit Applications

High-Throughput, Area-Efficient Architecture of 2-D Block FIR Filter Using Distributed Arithmetic Algorithm

Study of various data compression techniques used in lossless compression of ECG signals

Design of array multiplier circuit using reversible logic approach with optimized performance parameters

Design and fabrication of a nano patch electrode for ECG using CNT/PDMS