IEEE transactions on very large scale integration (VLSI) systems

In all the arithmetic operations, addition is one of the most important and initial operations used in most of the mathematical equations. The operation is performed by many adders present in the digital world. These adders give us carries with preferred delay and power. The three main features like structure, logic, and compact circuit layout help design a better adder. This Paper aims to analyse and compare various additions for high-speed, low-power and fast calculation. The various adder designs seen in digital signal processing applications require computationally efficient adding and cumulative operations, so blocks with the required attributes must be carefully selected. Various techniques have been proposed to design efficient adders in terms of performance, low power consumption and area. This work focused on 16-bit implementations of highly optimized area-efficient Ripple Carry Adders (RCA) and Look Ahead Carry Adders (LAC), and carry select Adder. Finally, we can prove that the Carry look ahead Adder is very fast in all existing designs. These processes are simulated and synthesized in all ISE Xilinx 14.7 software.

https://doi.org/10.1088/1757-899x/1224/1/012026

Performance Analysis of High Speed and Low Power Binary Adders

VLSI is an enduring technology which is used to change the entire digital element into autonomy, some real-time opportunities are characterized under Very Large Scale Integration such as low power application, testing, MOS technology etc. This research focused on signal processing in low power VLSI design, in existing system the backend IC fabrication process illustrates system-level design by using digital logic elecment. An existing digital element consist of different functions of adders such as carry select, ripple carry adder, carry skip adder, carry look ahead adder, which has consume more area, delay, and power. To improve the efficiency of digital design a novel majority carry save adder is proposed and incorporate with a structured tree multiplier, this research produce an optimized carry save adder design in digital filter for improve the signal to noise ratio. The proposed innovative carry save adder is constructed by using majority logic and implemented into a digital FIR filter, this new technique consumes low power, delay-free carry circuit and less number of gate counts. The proposed adder has achieved 96 % efficiency in terms of gate count, delay, and power compared with existing analysis. Digital system design produces 83.5 % efficiencyin an existing system and it required the maximum number of gate count and an increasing number of delays when compared with recent research. The design summary is analyzed by using XILINX 14.7 ISE synthesis and the implementation process is highly reached with the help of MATLAB 2018a. The proposed design is implemented into Biomedical Application for reducing noise and improving signal to noise ratio.

Anelegance of novel digital filter using majority logic on pipelined architecturefor SNR improvement in signal processing

Capricious Digital Filter Design and Implementation Using Baugh–Wooley Multiplier and Error Reduced Carry Prediction Approximate Adder for ECG Noise Removal Application

Recustomize finite impulse response (RFIR) filter is designed to achieve lesser power consume, cost, area, and higher speed of system operation. This is used to remove the noises from the image and signal. Previously, several filters were designed for removing noises, but that filters consume more area, power, cost, and delay and did not provide accurate results and the error rate was increased. To overcome these issues, this work is proposed. In this work, the Recustomize finite impulse response (RFIR) filter is designed using truncation‐based scalable rounding approximate multiplier (TOSAM) and error reduced carry prediction approximate adder (ERCPAA) for image processing application. Here, TOSAM‐ERCPAA is used to speed up the filter design with less area and less power consumption. The proposed ERCPAA adder is divided into three blocks, such as carry prediction logic, approximate full adder cells array, constant truncation along error lessening logic, which can reduce the power and area. The proposed RFIR‐ TOSAM‐ERCPAA filter is designed and executed in Verilog programming language and the simulation is done in Xilinx ISE 14.5 design tools.

Design of recustomize finite impulse response filter using truncation based scalable rounding approximate multiplier and error reduced carry prediction approximate adder for image processing application

In VLSI system design, one of the most significant areas of on-going research is high speed with low power system design. Usually the speed of the VLSI circuits like binary adders can be improved by more parallelism but, this more parallelism idea will increase the power consumption and area of the circuit. Therefore there is a trade-off between speed and power/area. A carry select adder is one of the fast binary adders but it consumes more power and area. In this paper, we proposed a low power and area efficient and high speed binary carry select adder (CSLA). The half sum and carry generator (HSCG) of the proposed CSLA is designed with a new methodology, that the HSCG output are estimated using input A and B not with carry-in hence it is faster and results in less area leads to low power consumption. Moreover, the NAND gate based circuit is used to compute the intermediate carries within the block and carry-out of the block which are derived from HSCG output along with carry-in. Similarly, the full sum of the proposed adder is generated from XNOR gate based circuitry by utilizing the intermediate carries of the block. The existing and proposed CSLAs are synthesized with the Synopsys EDA tool using 32 nm CMOS technology. The performance of the existing and proposed designs are analyzed and the results shows that the proposed 64-bit CSLA exhibits average reduction of 43% in power and average of 25% less utilization in terms of area compared to existing design. This proposed CSLA is used in a FIR Filter and obtained significant reduction in ADP and PDP.

Low power area optimized and high speed carry select adder using optimized half sum and carry generation unit for FIR filter

Background/Objectives : XOR gate is a primary element in binary adders because which is used to detect sum – output. In this paper a 2-input XOR gate is accomplished by a modified design. Methods/Statistical analysis : Usually a half adder (HA) circuit is designed with one XOR and one AND gate but if  this modified XOR is used in HA, the design requires only one XOR gate and the AND gate can be acquired from XOR gate itself. Findings: This modified XOR gate design gives better result when the adder circuit has more number of XOR gates, so we used this modified XOR gate in conventional sqrt CSLA, binary to excess-1 converter (BEC) based sqrt CSLA and optimized logic based (OLB) sqrt CSLA. The results show that Area – Delay – Product (ADP) has been reduced in proposed circuits, 12.45% in conventional sqrt CSLA, 21.45% in BEC based sqrt CSLA and 17.81% in OLB sqrt CSLA. Applications/Improvements: These adders can be used in Arithmetic Logic Unit (ALU) of a micro-processor as a binary adder.

Low - Power and Area - Efficient Square - Root Carry Select Adders using Modified XOR Gate

Decimal arithmetic is receiving greater attention due to its applications in banking and internet-based sectors. Several algorithms have been introduced for Multi-operand addition. A mixed approach of having binary adders followed by binary to BCD converter is showing better performance compared to binary adders with correction logic in intermediate stages. Adder circuits form the basis of our computing. Multiplication and division algorithms are also based on the adder circuits. Thus designing fast Multi-operand parallel adders is receiving greater interest by researchers. BD converters that are the final blocks of the adder circuits have gained a lot of importance highlighting the need to have an efficient BD converter as critical for improvised adder architectures. This paper proceeds with the mixed approach and it considers the special case of 8 operand decimal addition which is done using binary CSA structure and proposes a BD converter for 7-bit binary number that is efficient in terms of area and delay when compared to the existing designs. The power delay product of our design is 27% more efficient than existing designs.

Delay Optimized Binary to BCD Converter for Multi-operand Parallel Decimal Adder

In this paper, A Low Power Pre-charge Free Dynamic Content Addressable Memory is Proposed, it is one of the most significantly used Hardware search Engine in Modern Computing, Security Systems and in areas needing fast Memory Access. It is not only a Data Storage Device but also designed to search its own memory in single Cycle. The CAM is introduced in low power Parallel look up search Applications. A Proposed Low Power 6-T DCAM cell consuming power less than 93% and 43% than PF-DCAM and PF-CAM cells is introduced in Hardware Search Engine. 8*8 CAM Architecture of the proposed scheme is implemented using Cadence GPDK 45nm Technology.

Low Power Pre-Charge Free DCAM

Digital signal processing applications often use major mathematical operations such as multiplication, which consume more power and time. Operations like Fast Fourier Transform, Convolution and correlation depends heavily on a large number of multiplications. There are many techniques available to perform multiplications. One such technique is logarithmic multiplication. logarithmic multiplication is achieved by adding the binary logarithms of two numbers and deriving the antilog of the result. In this paper, an efficient algorithm for logarithmic multiplication is presented with the use of adders, decoders, multiplexers and a few combinational circuits that effectively reduce the power and area of the multiplier.

G. Ragunath

Papers

Low power area optimized and high speed carry select adder using optimized half sum and carry generation unit for FIR filter

Low - Power and Area - Efficient Square - Root Carry Select Adders using Modified XOR Gate

Delay Optimized Binary to BCD Converter for Multi-operand Parallel Decimal Adder

Low Power Pre-Charge Free DCAM

An Area Efficient 16-bit Logarithmic Multiplier