In the Current scenario of higher level of integration the most encountered problems are heat dissipation and information loss on each and every computation. For the sake of eliminating these issues Reversible computing is being adopted as a preferable substitute of digital circuit design. This paper focuses on the design of Reversible Ring Counter and Twisted Ring Counter using Reversible D flip flop implemented with the Novel Design of Feynman and Fredkin Gate. Ring counters are commonly found in applications used to count the data in a continuous loop as well as in frequency divider circuits. While twisted (or Johnson) ring counter is used as three-phase square wave generators (using 3 flip-flops) and quadrature oscillator circuits (using 2 flip-flops) etc. The response of the proposed counter circuit is tested with the help of QCADesigner 2.0.3 simulation tool and the Energy dissipation is analyzed by the use of QCA Designer-E tool.

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Reversible Shift Counter Design on QCA

In designing synchronous circuits and memory elements, Flip-flops (FF) play an integral role. In the present era, the demand of area efficient, lesser delay, and faster devices are the major concern. This paper present the comparative study of Flip Flops in terms of area and delay. The problem of device size is very dominant today because the demand for small device size along with lesser number of transistors is increasing. And also for implementing a circuit, comparatively less number of transistors are preferred in comparison to conventionally used number of transistors, as it results in lesser number of switching activities. And smaller delay is preferred as it results in faster device along with faster response time of device. Hence, in this paper, the comparative study of various flip flops using The Clocked CMOS (C2MOS) register, True Single-Phase Clocked Register (TSPCR), Self-Gating Flip Flop, Static Flip Flop is done. The reduction in the delay is done by properly changing the size of transistor and alteration in the value of voltage. The circuits are simulated and correlated using 45nm technology.

Analytical study of high performance flip-flop circuits based on performance measurements

Ensuring correct functionality is the basic objective of any digital design and this can be done only if the circuit obeys all the timing constraints. Static Timing Analysis is the procedure perfor...

Comprehensive Design and Timing Analysis for High speed Master Slave D Flip-Flops using 18 nm FinFET Technology

D-Flipflops are widely used in designing various analogue, digital and mixed signals. Different shift registers, counters and other circuits are designed using D-Flipflop. To increase the battery life time and reduce the power consumption, the voltage given to the circuit have to be decreased in the Standby mode of operation. In this paper different D Flipflops are designed using techniques like 5 transistor D-Flip Flop, Self-voltage level D-Flipflop and modified SVL (Self Voltage Level) D-Flipflop and Novel sleep transistor technique. Comparisons are made between all the designs in terms of power, delay and leakage power. All the designs are designed and simulated with the help of Cadence Virtuoso in 90nm technology. The leakage power observed in Novel Sleep Transistor technique is 93.5% less than that observed in Modified SVL Technique. 

Designing a D-Flipflop Using Novel Sleep Transistor Technique

Design For Testability (DFT) is a technique used while designing the Integrated Circuit (IC) to add features to the hardware design which helps in testing the design. Scan insertion is one of the DFT techniques which is used in sequential circuits. It is most popularly used as the testability of the circuit will be much better and the design can be easily tested. Scan insertion involves the insertion of scan flip-flop consisting of a D flip-flop with an extra multiplexer and additional scan input and scan output pins. The addition of extra circuitry increases the area, delay and power consumption which is undesirable. Hence, there is increase in the amount of silicon used and in the test time, which leads to lower profits. In this paper, two novel and efficient Scan flip-flop designs have been implemented consuming less power, area and delay. The two unique Scan flip-flop designs namely Gate Diffusion Input based D flip-flop and modified Transmission Gate based Scan flip-flop have been developed in Cadence Virtuoso. An improvement of 42.12% and 27.38% was observed in speed during functional and test modes respectively. A decrease of 47% and 56.73% was observed in peak-power consumption in functional and test modes respectively.

Designof Efficient Scan Flip-Flop

D flip flops are extensively used in analog, digital and mixed signal systems. D flip flops are first choice to realize different counters, shift registers and other circuits. One major consequence of scaling of CMOS technology is leakage power. To decrease power consumption and to improve life time of battery, the voltage supplied to the given circuit during standby mode should be reduced. This paper proposes a new D flip flop design which employs improved SVL technique in order to reduce power consumption due to leakage currents in standby mode. Also the proposed design uses less number of clocked transistors, thus reduces the dynamic power consumption as well as delay compared to existing design. Proposed design achieves 60.54% reduction in power delay product in comparison with existing D flip flop design. Both existing design and proposed design are simulated using Tanner T spice tool at 45nm technology.

G. Sushma

Papers

Low power high speed D flip flop design using improved SVL technique