Proceedings ArticleDOI
Low power high speed D flip flop design using improved SVL technique
G. Sushma,V. Ramesh +1 more
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TLDR
A new D flip flop design is proposed which employs improved SVL technique in order to reduce power consumption due to leakage currents in standby mode and uses less number of clocked transistors, thus reduces the dynamic power consumption as well as delay compared to existing design.Abstract:
D flip flops are extensively used in analog, digital and mixed signal systems. D flip flops are first choice to realize different counters, shift registers and other circuits. One major consequence of scaling of CMOS technology is leakage power. To decrease power consumption and to improve life time of battery, the voltage supplied to the given circuit during standby mode should be reduced. This paper proposes a new D flip flop design which employs improved SVL technique in order to reduce power consumption due to leakage currents in standby mode. Also the proposed design uses less number of clocked transistors, thus reduces the dynamic power consumption as well as delay compared to existing design. Proposed design achieves 60.54% reduction in power delay product in comparison with existing D flip flop design. Both existing design and proposed design are simulated using Tanner T spice tool at 45nm technology.read more
Citations
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Reversible Shift Counter Design on QCA
TL;DR: This paper focuses on the design of Reversible Ring Counter and Twisted Ring Counter using Reversible D flip flop implemented with the Novel Design of Feynman and Fredkin Gate.
Proceedings ArticleDOI
Analytical study of high performance flip-flop circuits based on performance measurements
Neha Raghav,Malti Bansal +1 more
TL;DR: The comparative study of various flip flops using The Clocked CMOS (C2MOS) register, True Single-Phase Clocked Register (TSPCR), Self-Gating Flipflop, Static Flip Flop is done.
Journal ArticleDOI
Comprehensive Design and Timing Analysis for High speed Master Slave D Flip-Flops using 18 nm FinFET Technology
TL;DR: In this paper, the Static Timing Analysis (STA) is used to ensure correct functionality is the basic objective of any digital design and this can be done only if the circuit obeys all the timing constraints.
Proceedings ArticleDOI
Designing a D-Flipflop Using Novel Sleep Transistor Technique
TL;DR: In this article , different D-Flipflops are designed using techniques like 5 transistor DFL, Self-voltage level D-FLOP, modified SVL (Self Voltage Level) DFLOP and Novel sleep transistor technique.
Proceedings ArticleDOI
Designof Efficient Scan Flip-Flop
B Nagesh,B S Nikhil Chandra +1 more
TL;DR: In this paper, two novel and efficient scan flip-flop designs have been implemented consuming less power, area and delay, and an improvement of 42.12% and 27.38% was observed in speed during functional and test modes respectively.
References
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Proceedings ArticleDOI
A unified approach in the analysis of latches and flip-flops for low-power systems
TL;DR: A new simulation and optimization approach is presented, targeting both high-performance and power budget issues, and the sources of performance and power consumption bottlenecks in different design styles are revealed.
Proceedings ArticleDOI
A Clock-Gated Pulse-Triggered D Flip-Flop for Low-Power High-Performance VLSI Synchronous Systems
TL;DR: A pulse-triggered D flip-flop with an embedded clock-gating scheme that is suitable for low-power high-speed synchronous applications is presented in this paper and leads to power savings around 45% when used to build a 16-bits binary counter.
Design of Flip-Flops for High Performance VLSI Applications using Deep Submicron CMOS Technology
TL;DR: This project proposes low power high speed design of flip flops in which True Single Phase Clocking (TSPC) and C2CMOS flip flop are compared with existing Flip-Flop topologies in term of its area, transistor count, power dissipation, propagation delay, parasitic values with the simulation results in microwind.
Proceedings ArticleDOI
Implementation of Low Power Flip Flop Design in Nanometer Regime
TL;DR: This paper has illustrated Single Edge Triggered 5T Delay flip flop design with leakage reduction technique in which the feedback path get removed that was present in the conventional Delay Flip Flop design, and shows a tremendous reduction in leakage power nearly by 68% at 1volt supply in comparison with the conventional Set-Reset latch based DFF.