This paper presents a unifying procedure, called Facet, for the automated synthesis of data paths at the register-transfer level. The procedure minimizes the number of storage elements, data operators, and interconnection units. A design generator named Emerald, based on Facet, was developed and implemented to facilitate extensive experiments with the methodology. The input to the design generator is a behavioral description which is viewed as a code sequence. Emerald provides mechanisms for interactively manipulating the code sequence. Different forms of the code sequence are mapped into data paths of different cost and speed. Data paths for the behavioral descriptions of the AM2910, the AM2901, and the IBM System/370 were produced and analyzed. Designs for the AM2910 and the AM2901 are compared with commercial designs. Overall, the total number of gates required for Emerald's designs is about 15 percent more than the commercial designs. The design space spanned by the behavioral specification of the AM2901 is extensively explored.

Automated Synthesis of Data Paths in Digital Systems

We present the Instruction Set Description Language,ISDL, a machine description language used to describetarget architectures to a retargetable compiler. The featuresand flexibility of ISDL enable the description of vastly differentarchitectures, in particular VLIW architectures. ISDL explicitlysupports constraints that define valid operation groupingswithin an instruction, increasing the range of specifiable architectures.We have written a tool that, given an ISDL descriptionof a processor, automatically generates an assembler forit. Ongoing work includes the development of an automaticcode-generator generator.

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ISDL: an instruction set description language for retargetability

The current status of a research program at Carnegie-Mellon University aimed at the formulation of a hierarchical design methodology for digital VLSI circuits is described In addition, this paper describes a set of computer aids which supports this methodology One of the goals of this work is to provide a design environment which allows for a significant reduction in time between the initial concept of a complex digital system and the generation of masks Another goal is to allow the designer to efficiently explore a number of design alternatives

A design methodology and computer aids for digital VLSI systems

This paper describes a method for formally modeling digital logic using algebraic relations. The relations model digital logic at the register-transfer (RT) level. An RT-level behaviorial specification is used to develop the relations, which express timing relationships that must be satisfied by any correct implementation. An extension of the model is shown which can be used for synthesis at the RT level. The growth rate and computational properties of the model are discussed, and an example of synthesis is shown.

A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic

specification. Digital system design actually consists of many synthesis steps, each adding detail. The quality of designs produced by automatic synthesis programs are not yet adequate for production use. However, their use as a computer aid permitting designer interaction is becoming a realitv, 1 and promises further

Automatic Data Path Synthesis

A top-down design method is presented. The design starts with an algorithmic description of the problems and attempts to find an optimal hardware structure for the solution of the problems. Comparisons with methods using hardware and functional descriptions are included. The application of the macro processor is explained.

G. Zimmermann

Papers

The Mimola Design System a Computer Aided Digital Processor Design Method