A computer program for execution on a computing device is provided to cross-train students in language development skills such as letter-word correspondence, word recognition, vocabulary, and sentence and paragraph comprehension. A set of programs provide an adaptive methodology for training a student in decoding (semantic, syntactic, phonological, and morphological relationships), knowledge of rhymes, synonyms, antonyms, and homophones, spelling, letter-word correspondences, sentence comprehension, grammatical comprehension, working memory, vocabulary, paragraph comprehension, and improved reading comprehension. In each program, students are presented with an animated scene that poses a question, and a set of answers. The set of answers contain a correct response, and a number of incorrect responses or foils. The student advances to more complex levels by satisfying predetermined correct thresholds. Through repetition and intensity, the student's language skills are developed.

Method and apparatus for automated training of language learning skills

A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Translated memory protection apparatus for an advanced microprocessor

A cache coherency protocol for a multi-processor system which provides for read/write, read-only and transitional data states and for an indication of these states to be stored in a memory directory in main memory. The transitional data state occurs when a processor requests from main memory a data block in another processor's cache and the request is pending completion. All subsequent read requests for the data block during the pendency of the first request are inhibited until completion of the first request. Also provided in the memory directory for each data block is a field for identifying the processor which owns the data block in question. Data block ownership information is used to determine where requested owned data is located.

Cache coherency protocol for multi processor computer system

A cache management system and method monitors and controls the contents of cache memory (12) coupled to at least one host (22a) and at least one data storage device (18a). A cache indexer (16) maintains a current index (25) of data elements which are stored in cache memory (12). A sequential data access indicator (30), responsive to the cache index (16) and to a user selectable sequential data access threshold, determines that a sequential data access is in progress for a given process and provides an indication of the same. The system and method allocate a micro-cache memory (12) to any process performing a sequential data access. In response to the indication of a sequential data access in progress and to a user selectable maximum number of data elements to be prefetched, a data retrieval requestor requests retrieval of up to the selected maximum number of data elements from a data storage device (18b). A user selectable number of sequential data elements determines when previously used micro-cache memory locations will be overwritten. A method of dynamically monitoring and adjusting cache management parameters is also disclosed.

System and Method for dynamically controlling cache management

A bus snoop control method for maintaining coherency between a write-back cache and main memory during memory accesses by an alternate bus master. The method and apparatus incorporates an option to source `dirty` or altered data from the write-back cache to the alternate bus master during a memory read operation, and simultaneously invalidate `dirty` or altered data from the write-back cache. The method minimizes the number of cache accesses required to maintain coherency between the cache and main memory during page-out/page-in sequences initiated by the alternate bus master, thereby improving system performance.

Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation

A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly, on a one-to-one basis maps a range of physical address bits into a first section of the operand cache storage. An associative directory multiply maps physical addresses outside of the range into a second section of the operand cache storage section. All stack frames of user programs to be executed on the time-shared basis are stored in the first section, so cache misses due to stack operations are avoided. An instruction cache haivng various categories of instructions stores a group of status bits identifying the instruction category with each instruction. When a context switch occures, only instructions of the category least likely to be used in the near future are cleared decreasing delays due to clearing of the instruction cache as a result of context switches. A page-mapped I/O cache structure interfaces by a large number of I/O channels which regard a single I/O cache as an exclusive buffer. System operating delays due to maintaining cache coherency, operand cache misses, instruction cache misses, I/O cache misses, and maintaining a cache coherency are substantially reduced.

Coherent cache structures and methods

A predictive arbitration system for interfacing a plurality of peripheral component interconnect (PCI) agents coupled to a first PCI bus with a second PCI bus. In one embodiment, the present predictive arbitration system includes a first PCI bus adapted to transmit data signals. A plurality of PCI agents are coupled to the first PCI bus. A predictive arbiter is coupled to both the first PCI bus and a second PCI bus. The predictive arbiter is also coupled to the plurality of PCI agents. The predictive arbiter is configured to receive requests for access to the first or second PCI bus from any of the plurality of PCI agents. The predictive arbiter, upon receiving requests for access, transmits one of the requests to a second arbiter coupled to the second PCI bus, wherein the selected and transmitted request originates from a selected one of the plurality of PCI agents. The predictive arbiter is also adapted to receive a grant signal from the second arbiter in response to the selected and transmitted request. The predictive arbiter further comprises a predictive arbitration system for enabling a grant line coupled to the selected one of the plurality of PCI agents before the grant signal is received from the second arbiter.

Predictive arbitration system for PCI bus agents

An apparatus and method for minimizing bus traffic by combining write operations is disclosed. The present invention detects the occurrence of consecutive byte updates to a common 32-bit block. This is accomplished by using comparators to examine the addresses of consecutive write operations. If it is determined that the consecutive write operations are indeed to a common 32-bit block, they are combined. The address of the next write operation is also, similarly checked. All of the writes into that particular block are combined in a write combine register. The contents of this register is then transferred to a write buffer. When bus access is granted, the combined byte updates stored in the write buffer are issued in a single memory write cycle to the bus, thereby minimizing the number of write cycles actually required to transfer the data.

Combined consective byte update buffer

A system and method for determining which of plurality of peripheral components will have access to a peripheral component interconnect (PCI) bus when none of the plurality of peripheral components is currently requesting access to the PCI bus. In one embodiment a history buffer records all requests by a plurality of peripheral components for access to the PCI bus. The present invention then determines which of the plurality of peripheral components requests access to the PCI bus most often. Next, the present invention grants the peripheral component which requests access to the PCI bus most often access to the PCI bus when no other peripheral component is requesting access to the PCI bus. In so doing, the present invention "parks" the PCI bus on the peripheral component which has, in the past, requested access to the PCI bus most often.

Adaptive arbitration mechanism for a shared multi-master bus

The present invention comprises a smart retry system for a PCI (peripheral component interconnect) agent in a PCI bus system. The system of the present invention includes an initiator PCI agent, a retry identification register, and a completion counter. The initiator PCI agent is adapted to couple to a PCI bus and communicate with a target PCI agent via the PCI bus by initiating a data transaction. The retry identification register is coupled to the initiator PCI agent. The retry identification register is adapted to store a target address and a transaction type corresponding to the target PCI agent when the target PCI agent issues a retry to the initiator PCI agent. The completion counter is coupled to the initiator PCI agent and is adapted to measure a latency period of the target PCI agent. The completion counter couples the latency period to the initiator PCI agent such that the initiator PCI agent efficiently completes a subsequent access corresponding to the target address and to the transaction type by initiating the subsequent access at the expiration of the latency period.

Gabriel Roland Munguia

Papers

Coherent cache structures and methods

Predictive arbitration system for PCI bus agents

Combined consective byte update buffer

Adaptive arbitration mechanism for a shared multi-master bus

Address dependent retry system to program the retry latency of an initiator PCI agent