J
Joseph C. Circello
Researcher at Motorola
Publications - 28
Citations - 1221
Joseph C. Circello is an academic researcher from Motorola. The author has contributed to research in topics: Cache & Operand. The author has an hindex of 14, co-authored 28 publications receiving 1221 citations. Previous affiliations of Joseph C. Circello include Freescale Semiconductor.
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Patent
Data processing system for performing a debug function and method therefor
TL;DR: In this article, a debug module of a data processor (3) provides a parallel output port for providing internal operating information via a DDATA signal and a PST signal, which allows an external development system (7) to dynamically observe internal operations of data processor without assuming a type or availability of an external bus and without significantly impacting the efficiency and speed of the data processor.
Patent
Serial scan chain architecture for a data processing system and method of operation
TL;DR: In this article, a scan chain architecture with a controller (10) and a multiplexer (24) is used to route test data through functional units (12, 14, 16, 18, 20, and 22).
Patent
Data processing system for controlling execution of a debug function and method therefor
TL;DR: In this article, the use of a bus (25) to communicate data, address, and control information between a core (9) and a debug module (10) allows debug module to have access the same internal registers and memory locations as central processing unit (2).
Patent
Superscalar processor with plural pipelined execution units each unit selectively having both normal and debug modes
TL;DR: In this paper, the authors propose a debug mode of a processor (10) which has a unique debug address space which executes instructions from the normal instruction set of the processor(10) without adversely affecting the state of the normal mode of operation while executing debug, test, and emulation commands at normal processor speed.
Patent
Coherent cache structures and methods
TL;DR: In this paper, a page-mapped I/O cache structure is proposed to reduce cache coherency in a multiprocessing system, which ensures that every access to a line of data is the most up-to-date copy of that line without storing cache-coherency status bits in a global memory and any reference thereto.