This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Realizations of voltage-mode and current-mode complex filters based on transconductance, transresistance, and current amplifiers for intermediate frequency (IF) applications are systematically developed. Various amplifiers are realized utilizing the second generation current conveyor (CCII) to promote comparisons at device levels. The adopted approach shows that the most efficient designs in terms of the number of active components are current-mode filters based on the transconductance and current amplifiers. As an application example, a 4th-order complex filter based on the CA is designed for low-IF Bluetooth receiver. Fabricated in a standard 0.18 μm CMOS technology, experimental results show that the proposed design offers improved characteristics over the available solutions in terms of power consumption and spurious-free dynamic range (SFDR). The filter exhibits in-band SFDR of 65.8 dB while consuming 1 mW.

/pdf/optimal-low-power-complex-filters-2gvk5nphoj.pdf

Optimal Low Power Complex Filters

A new wake-up receiver is proposed to reduce energy consumption and latency through adoption of two different data rates for the transmission of wake-up packets. To reduce the energy consumption, the start frame bits (SFBs) of a wake-up packet are transmitted at a low data rate of 1 kbps, and a bit-level duty cycle is employed for detection of SFBs. To reduce both energy consumption and latency, duty cycling is halted upon detection of the SFB sequence, and the rest of the wake-up packet is transmitted at a higher data rate of 200 kbps. The proposed wake-up receiver is designed and fabricated in a 0.18 μm CMOS technology with a core size of 1850×1560 μm for the target frequency range of 902-928 MHz. The measured results show that the proposed design achieves a sensitivity of -73 dBm, while dissipating an average power of 8.5 μW from a 1.8 V supply.

A new approach to low-power and low-latency wake-up receiver system for wireless sensor nodes = 무선 센서 노드를 위한 저전력 낮은 네트워크 지연을 갖는 웨이크업 수신기 시스템의 새로운 접근 방법

A fully differential Telescopic operational transconductance amplifier (OTA) and a sixth order Butterworth Gm-C low pass filter are presented in this paper. Both circuits are designed for medical applications in 2.4 GHz ISM band for IEEE 802.15.4 / ZigBee standard. The filter consists of three biquads. The design of the Telescopic OTA is carried out using two optimization methods, G m /I D and Particle Swarm Optimization (PSO) algorithm. Both circuits are implemented with TSMC 0.18 μm CMOS technology. Based on optimized OTA, the Gm-C filter has a cutoff frequency of 2.3 MHz and consumes only 1.55mW.

Design of sixth order butterworth Gm-C filter using Particle Swarm Optimization program for biomedical application

This paper presents a reconfigurable fifth-order complex Gm—C filter for different data rates in low-IF WiMAX applications. The design procedure and linearized measures to realize the complex filter are described. In order to achieve the reconfigurability of bandwidth window, the center frequency and the cutoff frequency filter are adjusted simultaneously by changing capacitor values while keeping transconductors unchanged. Also, the filter integrates an on-chip automatic frequency tuning circuit based on a PLL. Experimental results show that it has an IRR of 32 dB, a THD of −43 dB, and an input-referred noise of 21 μVrms. The chip is fabricated in 0.13 μm CMOS process, occupies 0.7 × 1 mm2, and consumes 4.8 mA current from a 1.2 V power supply.

A CMOS G m - C complex filter with a reconfigurable center and cutoff frequencies in low-IF WiMAX receivers

This paper presents a CMOS Gm—C complex filter for a low-IF receiver of the IEEE 802.15.4 standard. A pseudo differential OTA with reconfigurable common mode feedback and common mode feed-forward is proposed as well as the frequency tuning method based on a relaxation oscillator. A detailed analysis of non-ideality of the OTA and the frequency tuning method is elaborated. The analysis and measurement results have shown that the center frequency of the complex filter could be tuned accurately. The chip was fabricated in a standard 0.35 μm CMOS process, with a single 3.3 V power supply. The filter consumes 2.1mA current, has a measured in-band group delay ripple of less than 0.16 μs and an IRR larger than 28 dB at 2 MHz apart, which could meet the requirements oftheIEEE802.15.4 standard.

https://iopscience.iop.org/article/10.1088/1674-4926/32/7/075005/pdf

A pseudo differential G m —C complex filter with frequency tuning for IEEE802.15.4 applications

A PLL clock generator with reconfigurable multi-functions for FPGA design applications is presented. This clock generator has two configurable operation modes to achieve clock multiplication and phase alignment functions, respectively. The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable. In order to further improve the accuracy of phase alignment and phase shift, a VCO design based on a novel quick start-up technique is proposed. A new delay partition method is also adopted to improve the speed of the post-scale counter, which is used to realize the programmable phase shift and duty cycle. A prototype chip implemented in a 0.13-μm CMOS process achieves a wide tuning range from 270 MHz to 1.5 GHz. The power consumption and the measured RMS jitter at 1 GHz are less than 18 mW and 9 ps, respectively. The settling time is approximately 2 μs.

https://iopscience.iop.org/article/10.1088/1674-4926/32/4/045010/pdf

A 270-MHz to 1.5-GHz CMOS PLL clock generator with reconfigurable multi-functions for FPGA

A fully integrated super-regenerative wake-up receiver for wireless body area network applications is presented. The super-regeneration receiver is designed to receive OOK-modulated data from the base station. A low power waveform generator is adopted both to provide a quench signal for VCO and to provide a clock signal for the digital module. The receiver is manufactured in 0.18 μm CMOS process and the active area is 0.67 mm2. It achieves a sensitivity of −80 dBm for 10−3 BER with a data rate of 200 kbps. The power consumption of the super-regenerative wake-up receiver is about 2.16 mW.

http://iopscience.iop.org/article/10.1088/1674-4926/37/9/095001/pdf

A fully integrated CMOS super-regenerative wake-up receiver for EEG applications

This paper proposes a baseband circuit for wake-up receivers with double-mode detection and enhanced sensitivity robustness for use in the electronic toll collection system. A double-mode detection method, including amplitude detection and frequency detection, is proposed to reject interference and reduce false wake-ups. An improved closed-loop band-pass filter and a DC offset cancellation technique are also newly introduced to enhance the sensitivity robustness. The circuit is fabricated in TSMC 0.18 μm 3.3 V CMOS technology with an area of 0.12 mm2. Measurement results show that the sensitivity is −54.5 dBm with only a ±0.95 dBm variation from the 1.8 to 3.3 V power supply, and that the temperature variation of the sensitivity is ±1.4 dBm from −50 to 100°C. The current consumption is 1.4 to 1.7 μA under a 1.8 to 3.3 V power supply.

A baseband circuit for wake-up receivers with double-mode detection and enhanced sensitivity robustness

This paper presents a novel dual-band quadrature voltage controlled oscillator (VCO) with the gain proportional to the oscillation frequency. Frequency synthesizers with this VCO can reduce the bandwidth fluctuation over all the frequency ranges without compensation or calibration. Besides the original switched capacitor array, an extra switched varactor array is adopted for the implementation of the proposed VCO. The tuning technique of changing the values of the capacitor and varactor at the same ratio is also derived. For verification purposes, a 2.5 G/3.5 G dual-band quadrature VCO is fabricated in a 0.13 μm CMOS process for WiMAX applications. Measurement results show that the VCO gain is closely proportional to the oscillation frequency with ±16% variation over the entire frequency range. The phase noise is −138.15 dBc/Hz at 10 MHz from the 2.5 GHz carrier and −137.44 dBc/Hz at 10 MHz from the 3.5 GHz carrier.

http://iopscience.iop.org/article/10.1088/1674-4926/34/8/085002/pdf

Gao Tongqiang

Papers

A pseudo differential G m —C complex filter with frequency tuning for IEEE802.15.4 applications

A 270-MHz to 1.5-GHz CMOS PLL clock generator with reconfigurable multi-functions for FPGA

A fully integrated CMOS super-regenerative wake-up receiver for EEG applications

A baseband circuit for wake-up receivers with double-mode detection and enhanced sensitivity robustness

A dual-band quadrature VCO with gain proportional to oscillation frequency