G
Gaurav Saini
Researcher at National Institute of Technology, Kurukshetra
Publications - 60
Citations - 504
Gaurav Saini is an academic researcher from National Institute of Technology, Kurukshetra. The author has contributed to research in topics: Transconductance & Transistor. The author has an hindex of 10, co-authored 53 publications receiving 292 citations. Previous affiliations of Gaurav Saini include Oregon State University & Sharda University.
Papers
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Journal ArticleDOI
Stubble burning: Effects on health & environment, regulations and management practices
TL;DR: In this paper, it was estimated that about 352 Mt of stubble is generated each year in India out of which 22% and 34% are contributed by wheat and rice stubble respectively.
Journal ArticleDOI
Implementation of data intelligence models coupled with ensemble machine learning for prediction of water quality index
Sani Isah Abba,Quoc Bao Pham,Gaurav Saini,Nguyen Thi Thuy Linh,Ali Najah Ahmed,Meriame Mohajane,Mohammadreza Khaledian,R. A. Abdulkadir,Quang-Vu Bach +8 more
TL;DR: The results indicated the feasibility of the developed data intelligence models for predicting the WQI at the three stations with the superior modelling results of the NNE and demonstrated that NNE proved to be effective and can therefore serve as a reliable prediction approach.
Journal ArticleDOI
Use of natural coagulants for industrial wastewater treatment.
S. Gautam,Gaurav Saini +1 more
TL;DR: A state-of-the-art review of the natural coagulants' application in treating industrial wastewaters and their relative advantages and disadvantages as compared to the chemical coagULants is presented in this article.
Proceedings ArticleDOI
New low-power techniques: Leakage Feedback with Stack & Sleep Stack with Keeper
TL;DR: Two novel approaches from simulation study are proposed, named "Leakage Feedback with Stack (LFS)" & "Sleep Stack with Keeper (SSK)" which reduces leakage current while saving exact logic state and achieves up to 76–80 % less power consumption.
Journal ArticleDOI
Physical Scaling Limits of FinFET Structure: A Simulation Study
Gaurav Saini,Ashwani K. Rana +1 more
TL;DR: In this article, the scaling limits of double gate underlap and triple gate (TG) overlap FinFET structure using 2D and 3D computer simulations respectively, and it is found that the gate-length (L) and fin-thickness (T fin ) ratio plays a key role while deciding the performance of the device.