This paper presents a complete 50–64 Gb/s serializing transmitter including a 4-tap equalizer. An LC-based FFE structure is proposed. The FFE improves the bandwidth of the delay line and the output combiner by applying the design methodology of LC-ladder filters. Proper arrangement of the output combiner reduces the required number of inductors and hence reduces the area. In addition, a novel 4:1 multiplexer (MUX) is used as the final stage of the serializer to reduce power. Designed and fabricated in 65 nm CMOS technology, the transmitter achieves a maximum data rate of 64.5 Gb/s with an energy efficiency of 3.1 pJ/bit.

A 50–64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology

As processing and network speeds are accelerated to support data-rich services, the bandwidth of backplane interconnects needs to be increased while maintaining the channel length and multi-rate links. However, channel losses and impedance discontinuities increase at high data-rates, making it difficult to compensate the channel. In this work, we target serial links from auto-negotiation in 100G-KR4 of 0.3Gb/s to 32GFC of 28.05Gb/s in 40dB backplane architecture [1-3]. To achieve this challenge, there are two key techniques. First, we introduce a 36-tap decision-feedback equalizer (DFE) to cancel reflections due to connectors because these reflections close the eye. To operate the 36-tap DFE, we need to fix a CDR lock-point and calculate 36-tap coefficients accurately. Thus, we develop a pattern-captured CDR with a 4b pattern filter to fix the lock-point, and a 3b pattern-matched adaptive equalizer (AEQ) to optimize 36 tap coefficients. These techniques enable our chip to compensate 40dB channel loss. Second, we target 100G-KR4/40G-KR4/10G-KR/25G-KR and 32GFC/16GFC/8GFC/4GFC. To operate across a wide range of data-rates, from 0.3 to 28.05Gb/s, with low jitter, we develop a PLL architecture with two LC-VCOs and one ring VCO with a data-rate-adjustment technique by controlling an LDO. Our test chip is fabricated in 28nm CMOS. Our signal conditioner is the demonstration to achieve the BER <1012 PRBS31 at 100G-KR4 in a 40dB chip-to-chip backplane with two connectors by using the 36-tap DFE to cancel the reflection and to operate across a wide range of data-rates from 0.3 to 28.05Gb/s.

3.2 multi-standard 185fs rms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS

A half-duplex serial link design that is capable of 22 Gbps operation over PCB channels with up to 20 dB of loss is presented. A current-mode transmitter can be configured either as a pre-cursor or post-cursor 2-tap FIR filter. The receiver consists of a trans-admittance-trans-impedance single-stage linear equalizer that can provide 10 dB of high-frequency gain without the use of peaking inductors. The CTLE is followed by an half-rate 2-tap decision feedback equalizer with direct feedback. To mitigate long-tail intersymbol interference in a power-efficient manner, a third DFE tap employs a single-pole IIR filter. A 15-22 GHz LC-PLL provides quadrature clocks to a 16-lane macro. The 16-lane macro occupies 1.66 mm × 1.6 mm in a 28 nm CMOS process and is packaged in a 45 mm × 45 mm flip-chip MCM module. The link operates from two power supplies at 1.35 V and 0.9 V with a BER and a power efficiency of 6.5 mW/Gbps at 20 Gbps.

A 15–22 Gbps Serial Link in 28 nm CMOS With Direct DFE

A method comprises receiving an input signal at an input of a receiver and retrieving a data sample signal and an error sample signal from the input signal. The method also comprises applying an adaptive procedure to generate a feedback code using the data sample signal and the error sample signal for feeding back into a decision feedback equalization (DFE) module. Further, it comprises converting the feedback code into a corresponding voltage value and assigning the corresponding voltage value as a tap weight for the DFE module. Finally, it comprises generating an edge sample signal by applying DFE to the input signal using the DFE module, wherein the DFE is based on the tap weight.

Adaptation of crossing DFE tap weight

In an example, a clock data recovery (CDR) circuit for a receiver includes a timing error detector circuit, a loop filter, and a phase interpolator. The timing error detector circuit is coupled to receive, at a baud-rate, data samples and error samples for symbols received by the receiver. The timing error detector circuit is operable to generate both a timing error value and an estimated waveform value per symbol based on the data samples and the error samples. The loop filter is coupled to the timing error detector to receive timing error values. The phase interpolator is coupled to the loop filter to receive filtered timing error values, the phase interpolator operable to generate a control signal to adjust a sampling phase used to generate the data samples and the error samples.

Baud-rate CDR circuit and method for low power applications

As the processing power and clock rate of CPUs and GPUs increase, there is a need for increased I/O bandwidth to enable chip-to-chip communication. I/O pin limitations demand faster links at low power to enable integration of high chip-to-chip bandwidth. However, the channel losses and impedance discontinuities increase at high data rates making it difficult to equalize the channel at low power. In this work, we target reliable, differential, bi-directional links at 20 Gb/s over 6” FR4 PCB trace and flip-chip packages with a total loss budget of 20 dB at Nyquist. In a half-duplex link, one TX and RX are connected on each side and the link direction can be turned around by the controller. A link-turnaround latency of <;10 ns is achieved by placing several key circuits on standby when not in use and by designing fast bias circuits. When fast turnaround is not required, the circuits not in use are powered down permanently and the link is reduced to the simplex case. The top-level transceiver architecture is shown. An LC-VCO-based PLL oscillates at 20 GHz and generates quadrature I/Q clocks at 10 GHz. Both TX and RX use a half-rate architecture to optimize power. The clocks are distributed through an on-chip transmission line to 16 I/O lanes arranged in 2 rows. The links are capable of data rates as low as 14 Gb/s to save power when full bandwidth is not required.

26.1 A 130mW 20Gb/s half-duplex serial link in 28nm CMOS

One embodiment provides a data-receiving device component comprising a phase shifter, timer logic, and control logic. The phase shifter is configured to release a train of clock pulses with a controlled phase shift. The timer logic is configured to receive data from a data-sending device, and for each transition of the data received, to determine whether a clock pulse from the train is early or late with respect to the transition, and to tally the late clock pulses relative to the early clock pulses. The control logic, operatively coupled to the phase shifter and to the timer logic, is configured to incrementally advance the phase shift when the late clock pulses outnumber the early clock pulses by a non-integer power of two.

Flexible threshold counter for clock-and-data recovery

A method comprises adapting a first tap weight of an equalizer, wherein a second tap weight of the equalizer is based at least in part on the first tap weight. Adapting the first tap weight further comprises computing a gradient from a data signal, an error signal and a channel pulse response sample. Adapting the first tap weight also comprises filtering the gradient with a loop filter and sending information to a transmitter via a back channel. Adapting the first tap weight further comprises configuring the first tap weight based on the information.

Back channel adaptation for transmission under peak power constraints

Eine Daten empfangende Geratekomponente mit: einem Phasenschieber, der ausgebildet ist, eine Sequenz aus Taktpulsen mit einer gesteuerten Phasenverschiebung auszugeben; einer Zeitgeberlogik, die ausgebildet ist, nach jedem N-ten Taktzyklus Daten aus einem Daten sendenden Gerat zeitlich zu entschachteln in N zeitlich entschachtelte Datenleitungen, N > 1 und fur jeden Ubergang der N zeitlich entschachtelten Datenleitungen zu ermitteln, ob ein gleichlaufender Taktpuls aus der Sequenz fruh oder spat in Bezug auf den Ubergang liegt, und die spaten Taktpulse relativ zu den fruhen Taktpulsen zu zahlen; und einer Steuerlogik, die funktionsmasig mit dem Phasenschieber und der Zeitgeberlogik verbunden und ausgebildet ist, den Phasenschieber zu veranlassen, die Phasenverschiebung inkremental nach vorne zu verschieben, wenn bei einem Zahlerergebnis, dass uber N-Taktzyklen akkumuliert wurde die spaten Taktpulse um eine nicht ganzzahlige Potenz von zwei zahlreicher als die fruhen Taktpulse sind

Gautam Bhatia

Papers

Adaptation of crossing DFE tap weight

26.1 A 130mW 20Gb/s half-duplex serial link in 28nm CMOS

Flexible threshold counter for clock-and-data recovery

Back channel adaptation for transmission under peak power constraints

Flexibler Schwellwertzähler für Takt- und Datenwiederherstellung