A virtual address translator comprises a content addressed memory and a word addressed memory. A task name and subsegment number from a virtual address supplied by a processor are employed as a key word to search a content addressed memory and read out a subsegment descriptor if the key word is matched. The subsegment descriptor includes an absolute base address which is added to a deflection field to obtain an absolute memory address. The memory address is applied to a memory to permit transfer of a word between the processor and the memory. The processor may present any one of several task names depending upon whether the memory reference is made for an instruction or data for the processor, or for an instruction or data for an I/O connected to the processor. Bounds, residency and access privileges are checked using the subsegment descriptor. If a search of the content addressed memory reveals that the desired subsegment descriptor is not in the word addressed memory, the translator obtains the descriptor from memory and then generates the desired absolute memory address. The translator is provided with circuits generating values which indicate the efficiency of its operation. Controls are provided for selecting any one of several widths for the subsegment and deflection fields of virtual addresses received from the processor.

Virtual address translator

An intuitive precharge sequencing technique for improving memory access through elimination of delay time incurred through precharging during page mode access of DRAM type memory. Current and prior page address access request information is used to generate a prediction as to whether the next address request will cross a page boundary and, therefore, require precharging of a new page. The predicted new page is then precharged before access is requested. Further advantages are obtained by providing an enable/disable feature, which allows either software or hardware to initiate or deactivate the operation of the precharge request in association with current or historical operating characteristics for a particular processor or program tasks. Where desired or practical, multiple levels of predictive analysis are used to refine the accuracy of trend predictions.

Apparatus and method of addressing paged mode memory including adjacent page precharging

Disclosed is a memory system for reading and writing variable length data fields. Each of the data fields are addressed by the combination of a word address, a bit address, and a field length. Internal to the memory system, a total of 2N cells are addressed by each word address where N is the maximum field length. But only a portion of the addressed cells are selectively enabled in response to the bit address and field length. An N bit shifter right justifies the output data from the selectively enabled cells, and also realigns right justified input data to be written into the selectively enabled cells.

Bit addressable variable length memory system

The specification discloses a digital cryptographic system operating under a digital coding scheme having forbidden control characters with common bit characteristics. In the encoding mode, clear digital data and randomized digital data are stored and selected bits of the clear and randomized digital data are modulo-2 added. The added bits are then examined to determine whether or not the bits have the common bit characteristics of the forbidden control characters. If so, the selected bits of the stored clear digital data are varied to prevent the subsequent generation of forbidden control characters in the encoded data. The clear digital data and randomized digital data are then modulo-2 added to generate encoded data. The present system is compatible with eight-level digital codes and the system includes parity bit checking techniques to ensure accuracy of operation. The present system may be operated as either an On-line or Offline system and may be utilized to provide security of digital transmission between teleprinters or between a teleprinter and a digital computer or the like.

Digital cryptographic system and method

In a circuit arrangement for use in accessing selected address numbered with a preselected distance left between two adjacent ones of the selected addresses, a control circuit centralizes control operation of a switching network with reference to a reference one of the selected addresses and the preselected distance to make the switching network form internal paths between input and output port sets of the switching network. Alternatively, when ports of a selected one of the input and output port sets are accessed at a predetermined port interval, the control circuit controls the switching network with reference to the predetermined port interval and a reference port selected from the selected port set. A leading port of the other set is determined to be connected to the reference port. A rearranging circuit may be connected to one of the input and output port sets to rearrange an order of the ports of the one port set in consideration of the port distance. The reference and leading ports may be varied in a time division fashion when a conflict of internal paths otherwise occurs in relation to the port distance.

Circuit arrangement capable of centralizing control of a switching network

In a microprogrammed processor, a pair of register means and an associative store are arranged to eliminate the need to translate, for each microinstruction, a logical address to a real address to access main storage. Translation is required only once for each program or machine level (macro) instruction. The real addresses of the first bytes of the current instruction and its operand(s) are stored in a first one of the register means and are normally incremented to access the remainder of the instruction and operands byte-by-byte. In addition, the first register means and incrementer can be used to access sequentially stored instructions in a program sequence without address translation. When a page boundary is crossed during said incrementing, the logical page address of the current instruction or operand (which is at the boundary) is read from the second register means and is incremented to form the logical address of the next sequential page. This new logical address is searched in the associative array. If a match occurs, the new logical address is stored in the second register means, and the corresponding real address is stored in the first register means. This hardware translate means significantly reduces translate time.

Device for address translation

A circuit arrangement is provided for controlling a known logical switching network for shifting data of variable widths, wherein the shift amount by which the data bits applied to the input are to be shifted is switched from the true value to the complement value and vice versa by means of a control signal influenced by control commands, and wherein the partial results thus produced are logically combined to form a further partial result or the final result.

Shift unit for variable data widths

A parallel adder with sequential carry ripple is subdivided into sections. Detector circuits are distributed over the various digit positions of the adder. Each detector circuit receives the digit pairs of the input operands of at least one adder position. The detection circuits indicate the beginning or the end of a carry ripple chain by testing the condition "both input digits zero or both input digits one". Via a coder, the output signals of the detection circuits are combined in the form of group indicating signals, each of which corresponds to a predetermined distance between the digit positions. By means of the group indicating signals a clock circuit is controlled in such a manner that the operating time is limited to the time required for carry rippling.

Binary parallel computing arrangement for additions or subtractions

An error detecting and correcting system is provided for a unit having an essentially subordinate structure, such as a function unit of a computer. Correct output signals are assumed for the unit and, accordingly, check bits are formed as a function of the output signals of the unit. These bits are stored with a control word associated with each operation. As the operation is being executed, the check bits are regenerated from the output signals of the function unit and are subsequently compared with the correct check bits previously stored. Non-concurrence of the check bits indicates that an error may have occurred in the unit.

Geng Hellmuth R

Papers

Device for address translation

Shift unit for variable data widths

Binary parallel computing arrangement for additions or subtractions

Error detection and correction for data processing systems

Einrichtung zur fehlererkennung und -korrektur in elektronischen datenverarbeitungssystemen