Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.

Position independent testing of circuits

A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.

Testing buffer/register

Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Scan circuit low power adapter with counter

A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register (34), test port (38) and output control circuits (42, 46) controlled by an event qualifying module (EQM) (32). In response to a matching condition the EQM (32) may perform a variety of tests on incoming data while the integrated circuits (10, 12) continue to operate at speed. A plurality of digital bus monitors (20, 22) may be cascaded for observation and test of variable width data buses and variable width signature analysis.

Digital bus monitor integrated circuits

IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

Selecting different 1149.1 TAP domains from update-IR state

A digital to analog converter (DAC) for converting a digital signal (DS) having a maximum voltage range which corresponds to a first supply voltage (UL) into an analog signal (UOUT) having a maximum voltage range which corresponds to a second supply voltage (UH). The first supply voltage (UL) is offered between a first supply terminal (VSS) and a second supply terminal (VDDL). The second supply voltage (UH) is offered between the first supply terminal (VSS) and a third supply terminal (VDDH). The digital to analog converter (DAC) comprises conversion resistors (RCNV0 - RCNVn) and coupling means (CPL) for coupling a number of said conversion resistors (RCNV2 - RCNVn) in between the first supply terminal (VSS) and an output terminal (OUT), and for coupling the remainder of said conversion resistors (RCNV0 - RCNV1) in between the third supply terminal (VDDH) and the output terminal (OUT). The value of said number depends on the data content of the digital signal (DS). Digital to analog converters are generally implemented in ICs. For modern ICs there is a trend toward ever decreasing supply voltages. Often circuits implemented in new IC processes have to be able to interface with ICs processed in less modern processes which are generally operated on higher supply voltages. In the modern process, therefore, circuits designed in modern ICs have to cope with voltages which are above the maximum specification for their transistors or other components. The DA-converter (DAC) mentioned above fulfils this requirement by the fact that material, such as polycrystalline silicon, is used for the conversion resistors (RCNV2 - RCNVn), which material can cope with relatively high voltages, and furthermore by the fact that only the coupling means (CPL) have to be designed to cope with relatively high voltages.

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Digital to analog converter

An electrical counter including a pair of counter segments connected in cascade. Each of the counter segments has a capacity of two bits and counts in Gray code of 00, 01, 11, 10 and 00 on succeeding pulses to be counted which are applied onto the segment. The second segment includes an AND circuit which is satisfied when the count of the preceding segment is 10 so as to GATE the pulse supplied at that time on to the second segment so that the second segment has its value changed at the same time as the first segment has its value changed from 10 to 00.

Counter including two 2 bit counter segments connected in cascade each counting in Gray code

Utilizing predicted parity

Data processing apparatus constructed in shift register logic is provided in a simple manner with an optional pulse counting function by incorporating additional switching logic (64) into a linear shift register of sequential stages [SRL 0, 1, 2, 3] thereof, the additional logic (64) being responsive to a pulse input (C CLOCK), a count enable input and the current stage of the stages to force Grey code pattern shifting within separate groups (COUNTER SEG 1, 2) of sequentially adjacent stages and pulse advance between each sequentially adjacent pair of the groups at the termination of each Grey code pattern cycle in the leading group of the pair Both the linear shift function and the counting function are provided with the worst case inter stage connection spanning no more than a group

George Clark Thomas

Papers

Digital to analog converter

Counter including two 2 bit counter segments connected in cascade each counting in Gray code

Utilizing predicted parity

Two-mode-shift register/counter device