G
George W. Hawkins
Researcher at Motorola
Publications - 14
Citations - 445
George W. Hawkins is an academic researcher from Motorola. The author has contributed to research in topics: Die (integrated circuit) & Substrate (printing). The author has an hindex of 8, co-authored 14 publications receiving 445 citations.
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Patent
Flexible substrate for packaging a semiconductor component
Prosanto K. Mukerji,Ronald E. Thomas,George W. Hawkins,Rajesh Srinivasan,Colin B. Bosch,James H. Knapp,Laura J. Norton,Michael J. Seddon +7 more
TL;DR: A semiconductor component includes a semiconductor chip ( 341, 502, 601, 701, 1101, 1410, 1501 ) having first and second surfaces opposite each other as discussed by the authors.
Patent
Semiconductor chip bonded to a substrate and method of making
TL;DR: In this article, a semiconductor chip is flip-bonded to a substrate having a cavity or a through hole formed therein, and the cavity or through hole is preferably large enough to substantially remove the narrow gap which is formed between the portion of the substrate which does not have the cavities or through holes formed therein.
Patent
Method for making a moisture resistant semiconductor device having an organic substrate
Howard M. Berg,Sankaranarayanan Ganesan,Gary L. Lewis,George W. Hawkins,James W. Sloan,Scott C. Bolton +5 more
TL;DR: In this paper, a silicone-based die attach material is dispensed and gelled very soon after dispensing to prevent excessive bleed, and a semiconductor die is mounted to the substrate after undergoing a cleaning operation to remove contaminants from the backside of the die.
Patent
Semiconductor package having leads that break-away from supports
TL;DR: In this paper, the authors proposed a method for consistent alignment of flexible leads to reduce thermal stress caused by the differing coefficients of thermal expansion of a semiconductor package and a printed circuit.
Patent
Flagless semiconductor package
TL;DR: In this article, a molded semiconductor package having a flagless leadframe is presented, wherein a semiconductor die is disposed in or above a die opening of a leadframe.