G
Giacomo Valente
Researcher at University of L'Aquila
Publications - 31
Citations - 167
Giacomo Valente is an academic researcher from University of L'Aquila. The author has contributed to research in topics: Design space exploration & Mixed criticality. The author has an hindex of 7, co-authored 29 publications receiving 142 citations.
Papers
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Proceedings Article
Hardware performance sniffers for embedded systems profiling
TL;DR: This work deals with techniques to profile computational behavior and communication patterns of hardware/software components belonging to systems with multiple processing elements, i.e. a more general representation of on-chip embedded systems.
Proceedings ArticleDOI
A Flexible Profiling Sub-System for Reconfigurable Logic Architectures
Giacomo Valente,Vittoriano Muttillo,Luigi Pomante,Fabio Federici,Marco Faccio,A. Moro,S. Ferri,Carlo Tieri +7 more
TL;DR: This paper introduces "Adaptive Profiling Hardware Sub-system" (AIPHS), a hardware profiling tool supporting the development of runtime monitorable systems and two different multicore platforms are considered in order to evaluate AIPHS functionalities.
Journal ArticleDOI
Dynamic Partial Reconfiguration Profitability for Real-Time Systems
TL;DR: This letter presents the characterization of its reconfiguration cost in terms of time and a definition of the “DPR Profitability” concept targeting real-time systems, and validate the approach on a real DPR-compliant platform, showing that it is general enough to be applied to modern DPR- Compliant platforms.
Proceedings ArticleDOI
HEPSYCODE-RT: a Real-Time Extension for an ESL HW/SW Co-Design Methodology
TL;DR: This work focuses on the definition of a methodology for handling embedded real-time applications, starting from an existing HW/SW co-design methodology able to support the design of dedicated heterogeneous parallel systems.
Journal ArticleDOI
SPOF—Slave Powerlink on FPGA for Smart Sensors and Actuators Interfacing for Industry 4.0 Applications
Giacomo Valente,Vittoriano Muttillo,Mirco Muttillo,Gianluca Barile,Alfiero Leoni,Walter Tiberti,Luigi Pomante +6 more
TL;DR: This work provides a framework that supports the interfacing between the POWERLINK protocol and commonly used standards, such as I2C, SPI, and UART, by using a framework built around a soft IP-core Application Processor.