ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

ESD in silicon integrated circuits

This paper describes a constant impedance transmission line pulse system with new measurement capabilities and improved accuracy. The paper enforces a broader look at transmission line pulse (TLP) data, beyond the I-V curves. Accurate TLP measurements and actual TLP/HBM device data are used to demonstrate dV/dt effects and HBM/TLP correlation and miscorrelation. Finally, a calibration method and standard TLP test method are presented for adaptation by the industry. This is necessary to provide correlation and repeatability of experimental data.

/pdf/tlp-calibration-correlation-standards-and-new-techniques-34d3icfrbr.pdf

TLP calibration, correlation, standards, and new techniques

Electrostatic discharge (ESD) is an event that sends current through an integrated circuit (IC). This paper reviews the impact of ESD on the IC industry and details the four stages of an ESD event: (1) charge generation, (2) charge transfer, (3) device response, and (4) device failure. Topics reviewed are charge generation mechanisms, models for ESD charge transfer, electrical conduction mechanisms, and device damage mechanisms leading to circuit failure.

Electrostatic discharge in semiconductor devices: an overview

A novel diode-triggered silicon-controlled rectifier (DTSCR) (Mergens et al., 2003) electrostatic discharge (ESD) protection element is introduced for low-voltage application (signal and supply voltages /spl les/ 1.8 V) with extremely narrow ESD design margins. Trigger-voltage engineering in conjunction with fast and efficient SCR voltage clamping is applied for the protection of ultrasensitive circuit nodes, such as SiGe heterojunction bipolar transistor (HBT) base regions (e.g., f/sub Tmax/=45 GHz in BiCMOS 0.35-/spl mu/m LNA input) and thin gate oxides (e.g., t/sub ox/=1.7 nm in CMOS 0.09-/spl mu/m high-speed input). Ultrathin gate protection requires a reinforced trigger diode chain to avoid SCR trigger-speed issues resulting in critical trigger-voltage overshoots for very fast ESD transients such as a charged device model (CDM). SCR integration can be realized based on parasitic n-p-n/p-n-p inherent to CMOS devices or can alternatively be implemented based on vertical high-speed SiGe HBT with adjacent p+ SCR anode.

Speed optimized diode-triggered SCR (DTSCR) for RF ESD protection of ultra-sensitive IC nodes in advanced technologies

Time-dependent dielectric breakdown of 2.2-4.7 nm gate oxides is investigated down to the nanosecond time regime. The so-called 1/E model best fits the time-to-breakdown data. Latent damage is also examined and it is seen that the trap generation rate, i.e. the damage rate, is pulse-width dependent; and, thus, DC data should not be used to predict the degradation rate under ESD-type stress conditions. Voltage overshoots and a slow turn-on time make LVTSCRs bad candidates for protecting the ultra-thin gate oxide against CDM stress.

Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions

Transmission line pulsing (TLP) is well-established for the IV-characterization of ESD-protection elements. There still is a significant gap between the performance of present TLP-systems and the demands of the Charged Device Model (CDM). A very-fast, narrow-pulse (>3.5 ns), high-current TLP (VF-TLP) is designed to reduce this gap. It is feasible to study the pulsed breakdown of gate oxides and to determine at least the quasi-static IV-characteristics of input structures. Gate oxide breakdown is monitored within the first 6 ns of stress. Correlation with nn-CDM tests is achieved in terms of the failure signature. However, the failure thresholds of VF-TLP and nn-CDM do not correlate.

Gieser

Papers

Very-fast transmission line pulsing of integrated structures and the charged device model