Proceedings ArticleDOI
Very-fast transmission line pulsing of integrated structures and the charged device model
Gieser,Haunschild +1 more
- pp 85-94
TLDR
In this paper, gate oxide breakdown is monitored within the first 6 ns of stress in a very fast, narrow-pulse (>3.5 ns), high-current transmission line pulsing (VF-TLP) system.Abstract:
Transmission line pulsing (TLP) is well-established for the IV-characterization of ESD-protection elements. There still is a significant gap between the performance of present TLP-systems and the demands of the Charged Device Model (CDM). A very-fast, narrow-pulse (>3.5 ns), high-current TLP (VF-TLP) is designed to reduce this gap. It is feasible to study the pulsed breakdown of gate oxides and to determine at least the quasi-static IV-characteristics of input structures. Gate oxide breakdown is monitored within the first 6 ns of stress. Correlation with nn-CDM tests is achieved in terms of the failure signature. However, the failure thresholds of VF-TLP and nn-CDM do not correlate.read more
Citations
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Book
ESD in silicon integrated circuits
TL;DR: ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESC in Integrated Circuits Effects of Processing and Packaging.
Journal ArticleDOI
TLP calibration, correlation, standards, and new techniques
TL;DR: In this article, a constant impedance transmission line pulse (TLP) system with new measurement capabilities and improved accuracy is described, and a calibration method and standard TLP test method are presented for adaptation by the industry.
Journal ArticleDOI
Electrostatic discharge in semiconductor devices: an overview
J.E. Vinson,Juin J. Liou +1 more
TL;DR: In this article, the impact of ESD on the IC industry and details the four stages of an ESD event: (1) charge generation, (2) charge transfer, (3) device response and (4) device failure.
Journal ArticleDOI
Speed optimized diode-triggered SCR (DTSCR) for RF ESD protection of ultra-sensitive IC nodes in advanced technologies
Markus Paul Josef Mergens,Cornelius Christian Russ,K. Verhaege,John Armer,Phillip Czeslaw Jozwiak,Russell Mohn,B. Keppens,Cong-Son Trinh +7 more
TL;DR: In this paper, a diode-triggered silicon-controlled rectifier (DTSCR) was introduced for low-voltage application (signal and supply voltages /spl les/ 1.8 V) with extremely narrow ESD design margins.
Proceedings ArticleDOI
Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions
TL;DR: In this article, the 1/E model best fits the time-to-breakdown data and showed that the trap generation rate is pulse-width dependent; and thus, DC data should not be used to predict the degradation rate under ESD-type stress conditions.
References
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Journal ArticleDOI
Influence of tester, test method, and device type on CDM ESD testing
TL;DR: In this paper, the authors compared the characteristic waveforms defined by the EOS/ESD CDM ESD draft standard (DS5.3-1993), and some major problems related to the specification of socketed CDM testers are discussed.
Journal ArticleDOI
A correlation study between different types of CDM testers and "real" manufacturing in-line leakage failures
TL;DR: In this article, field-induced noncontact and socketed CDM testers correctly identified the weakest pins in a 0.8-/spl mu/m CMOS technology device.
Journal ArticleDOI
A CDM-only reproducible field degradation and its reliability aspect
TL;DR: In this paper, simulated electrostatic discharges (ESD) according to the human body model (HBM) and the charged device model (CDM) were compared in their ability to reproduce a leakage degradation observed in the field.
ESD monitor circuit : A tool to investigate the susceptibility and failure mechanisms of the charged device model
TL;DR: In this paper, the performance of protection elements is studied by means of transmission line pulsing, electron beam probing and non-contact, non-socketed CDM tests, and the capacitance connected to the source of the protection transistor and the resistance of this connection are critical.