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Gigy Baror
Researcher at Advanced Micro Devices
Publications - 30
Citations - 832
Gigy Baror is an academic researcher from Advanced Micro Devices. The author has contributed to research in topics: Graphics & Central processing unit. The author has an hindex of 13, co-authored 30 publications receiving 832 citations. Previous affiliations of Gigy Baror include Siemens & Infineon Technologies.
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Patent
Organization of an integrated cache unit for flexible usage in cache system design
TL;DR: In this article, the authors present a user-oriented approach to flexible cache system design by specifying desired cache features through the setting of appropriate cache option bits, which allows a high performance cache system to be designed with few parts, at low cost and with the ability to perform with high efficiency.
Patent
Organization of an integrated cache unit for flexible usage in supporting microprocessor operations
TL;DR: In this paper, a cache block status field is provided for each cache block to indicate the cache block's state, such as shared or exclusive, when a write hit access to the block occurs, which can be updated by either a TLB write policy field contained within a translation look-aside buffer entry, or by a second input independent of the TLB entry which may be provided from the system on a line basis.
Patent
Streamlined instruction processor
Gigy Baror,Brian Case,Rod Fleck,Philip M. Freidin,Smeeta Gupta,William M. Johnson,Cheng-Gang Kong,Ole Moller,Timothy Alan Olson,David I. Sorensen +9 more
TL;DR: In this article, a streamlined instruction processor is proposed to process data in response to a program composed of prespecified instructions in pipeline cycles, which includes an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions from the instruction memory.
Patent
Programmable cache memory as well as system incorporating same and method of operating programmable cache memory
Gigy Baror,William M. Johnson +1 more
TL;DR: In this article, an integrated cache unit (ICU) comprising both a cache memory and a cache controller on a single chip is presented. Butler et al. proposed an ICU that supports high speed data and instruction processing applications in both RISC and non-RISC architecture environments.
Patent
High performance processor interface between a single chip processor and off chip memory means having a dedicated and shared bus structure
William M. Johnson,Gigy Baror +1 more
TL;DR: In this paper, the authors describe a high performance interface between a processor and a set of devices, including memory means, including a shared processor output address bus, a processor input instruction bus, and a bidirectional data bus.