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Interacting with paper on the DigitalDesk

A voltage converting circuit of the charge pump step-up type includes a first circuit means for charging each of first and second capacitors with the voltage of a voltage source at a first timing. A second circuit operates to serially connect the charged first capacitor between a positive electrode of the voltage source and a positive voltage output terminal at a second timing so that a positive voltage which is a double of the voltage source voltage, is supplied from positive voltage output terminal. A third circuit operates to the charged first and second capacitors in series between a ground terminal and a negative voltage output terminal at a third timing so that a negative voltage which is a double of the voltage source voltage, is supplied from the negative voltage output terminal. Since the positive voltage and the negative voltage are generated independently of each other, a voltage variation on one of the positive and negative voltage output terminals caused by an external load causes no voltage variation on the other of the positive and negative voltage output terminals.

Voltage converting circuit and multiphase clock generating circuit used for driving the same

A temporally redundant latch for use in integrated circuit (IC) devices redundantly samples data output from logic or other circuitry at multiple time-shifted periods to provide multiple, independent data samples from which a correct data sample can be selected. The latch has three sampling circuits (e.g., D flip-flops or DICE latches) that sample the logic data output at three different and distinct sampling times. The latch also has a sample release circuit coupled to the sampling circuits to select and output a majority of the samples collected by the sampling circuits at a fourth time that again is different and distinct from the three sampling times. The latch affords both spatial parallelism due to the multiple parallel sampling circuits and temporal parallelism resulting from the clocking scheme involving multiple time-spaced clock signals. The temporally redundant latch is immune to upsets that might occur in the latch itself, as well as upsets that occur in the circuitry and upsets that might occur in any clocking and control signals on the IC device.

Temporally redundant latch for preventing single event disruptions in sequential integrated circuits

A communication client is connected to multiple display servers. When a client of one of the display servers issues a communication, the communication client notes the communication in the display server coupled to the client and relays the communication to the other servers for use by clients of the other servers.

System and method for communication between windowing environments

A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.

Circuit, system and method for controlling read latency

A phase-selectable flip-flop has an input dual-enable transparent latch and an output D-type flip-flop. A clock is input to one enable of the transparent latch and to the flip-flop, and a command is input to the second enable of the transparent latch. When the command is in a first state the latch is held transparent and data is clocked into the flip-flop on the rising edge of the clock, and when the command is in a second state data is held by the transparent latch on the falling edge of the clock and clocked into the flip-flop on the succeeding rising edge.

Phase-selectable flip-flop

The X11 Inter-Client Communication Conventions Manual (ICCCM) is a part of the X Window System standard. It provides guidelines for developers of interoperable X clients in a multi-vendor X system environment. This paper gives an overview of the rationale, goals, design constraints and content of version 1.0 of the ICCCM

Glenn F. Widener

Papers

Phase-selectable flip-flop

The X11 inter-client communication conventions manual